PATTGEN Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	168.579us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	5.000s	83.064us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	5.000s	13.109us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	133.218us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	5.000s	70.481us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	5.000s	31.229us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	5.000s	13.109us	20	20	100.00
		pattgen_csr_aliasing	5.000s	70.481us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.017m	13.598ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.367m	2.633ms	50	50	100.00
V2	error	pattgen_error	5.000s	18.677us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.083m	95.105ms	27	50	54.00
V2	alert_test	pattgen_alert_test	5.000s	23.054us	50	50	100.00
V2	intr_test	pattgen_intr_test	5.000s	20.848us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	87.471us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	87.471us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	5.000s	83.064us	5	5	100.00
		pattgen_csr_rw	5.000s	13.109us	20	20	100.00
		pattgen_csr_aliasing	5.000s	70.481us	5	5	100.00
		pattgen_same_csr_outstanding	6.000s	62.034us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	5.000s	83.064us	5	5	100.00
		pattgen_csr_rw	5.000s	13.109us	20	20	100.00
		pattgen_csr_aliasing	5.000s	70.481us	5	5	100.00
		pattgen_same_csr_outstanding	6.000s	62.034us	20	20	100.00
V2		TOTAL			317	340	93.24
V2S	tl_intg_err	pattgen_tl_intg_err	5.000s	133.152us	20	20	100.00
		pattgen_sec_cm	4.000s	67.088us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	5.000s	133.152us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	2.250m	16.998ms	3	50	6.00
V3		TOTAL			3	50	6.00
	Unmapped tests	pattgen_inactive_level	4.133m	10.020ms	41	50	82.00
		TOTAL			491	570	86.14

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	98.50	96.61	--	100.00	90.73

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:891) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:

Test pattgen_stress_all_with_rand_reset has 47 failures.

0.pattgen_stress_all_with_rand_reset.114672631161126222286333448049665360164092340106756261227227243574810960599958
Line 160, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1488722320 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1488728541 ps: (cip_base_vseq.sv:795) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1488728541 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 1488780626 ps: (cip_base_vseq.sv:819) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.91684919091901907994830355274630912235106482685307984717002917108308477337703
Line 112, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 521585950 ps: (cip_base_vseq.sv:891) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 521586565 ps: (cip_base_vseq.sv:795) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 521586565 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 521646565 ps: (cip_base_vseq.sv:819) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 45 more failures.

UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 23 failures:
- Test pattgen_stress_all has 23 failures.
  - 2.pattgen_stress_all.63451875556228779655446502988431904348800332327552341420708558833002364205370
    Line 146, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 2748283001 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10146
```
  - 5.pattgen_stress_all.50146947861544469439518641463463196331643929063289386829850170357908222270829
    Line 127, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_stress_all/latest/run.log
```
  UVM_ERROR @ 455727163 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @10333
```
  - ... and 21 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 5.pattgen_inactive_level.98866886707689742290650534995659317229985791567806818586384237903943387139766
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10087168935 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x90a60790, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10087168935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 45.pattgen_inactive_level.107863103951504472387772033235266845160873398234858767025715198975521595324974
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10020298560 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc2f93c50, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10020298560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 7.pattgen_inactive_level.17876416183599412036793768483913360797634225916971125453401456148784989781577
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10687378639 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x59256310, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
  UVM_INFO @ 10687378639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 12.pattgen_inactive_level.90389702964582736757677702001719220568630526202560746119474656884983547286704
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010625718 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x11d14350, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10010625718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 13.pattgen_inactive_level.49750073366227050925407916537939792898899954326903358829900717371447517216032
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10042802980 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf07184d0, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
  UVM_INFO @ 10042802980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 17.pattgen_inactive_level.105050847213403323233242240681228885525761624197081931076835712464136222331599
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10006864946 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x774cded0, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10006864946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 19.pattgen_inactive_level.5385050565718017457912775335808446182664204456835131329316924954528883114034
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10056686493 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xa87c7d10, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
  UVM_INFO @ 10056686493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 27.pattgen_inactive_level.52158201230414053826066726727944687727199737984406033978665218853559738194253
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10109873562 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x96b882d0, Comparison=CompareOpEq, exp_data=0x0, call_count=22)
  UVM_INFO @ 10109873562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 30.pattgen_inactive_level.93633968812502985063734578597974494874307423273438020403948297091672981693399
    Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10035410901 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x6f252e90, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
  UVM_INFO @ 10035410901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```