PWM Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: 27fc640f8d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	9.000s	533.761us	10	10	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	4.000s	28.178us	5	5	100.00
V1	csr_rw	pwm_csr_rw	5.000s	32.773us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	9.000s	335.866us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	51.651us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	5.000s	143.005us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	5.000s	32.773us	20	20	100.00
		pwm_csr_aliasing	5.000s	51.651us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	dutycycle	pwm_rand_output	1.050m	22.825ms	25	25	100.00
V2	pulse	pwm_rand_output	1.050m	22.825ms	25	25	100.00
V2	blink	pwm_rand_output	1.050m	22.825ms	25	25	100.00
V2	heartbeat	pwm_rand_output	1.050m	22.825ms	25	25	100.00
V2	resolution	pwm_rand_output	1.050m	22.825ms	25	25	100.00
V2	multi_channel	pwm_rand_output	1.050m	22.825ms	25	25	100.00
V2	polarity	pwm_rand_output	1.050m	22.825ms	25	25	100.00
V2	phase	pwm_rand_output	1.050m	22.825ms	25	25	100.00
		pwm_phase	1.233m	55.260ms	25	25	100.00
V2	lowpower	pwm_rand_output	1.050m	22.825ms	25	25	100.00
V2	perf	pwm_perf	1.017m	10.993ms	10	10	100.00
V2	regwen	pwm_regwen	2.817m	210.001ms	1	1	100.00
V2	stress_all	pwm_stress_all	3.550m	43.008ms	4	25	16.00
V2	alert_test	pwm_alert_test	5.000s	14.067us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	107.212us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	107.212us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	4.000s	28.178us	5	5	100.00
		pwm_csr_rw	5.000s	32.773us	20	20	100.00
		pwm_csr_aliasing	5.000s	51.651us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	55.690us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	4.000s	28.178us	5	5	100.00
		pwm_csr_rw	5.000s	32.773us	20	20	100.00
		pwm_csr_aliasing	5.000s	51.651us	5	5	100.00
		pwm_same_csr_outstanding	5.000s	55.690us	20	20	100.00
V2		TOTAL			155	176	88.07
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	523.063us	20	20	100.00
		pwm_sec_cm	4.000s	165.519us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	523.063us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	heartbeat_wrap	pwm_heartbeat_wrap	1.117m	29.373ms	10	10	100.00
V3		TOTAL			10	10	100.00
		TOTAL			255	276	92.39

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.90	99.42	99.04	99.59	97.91	90.87	--	100.00	99.67

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:452) [pwm_common_vseq] Check failed (intr_csrs.size() > *) Called intr_test vseq without any interrupt register. has 21 failures:
  • Test pwm_stress_all has 21 failures.

    • 0.pwm_stress_all.101508432063988856173421485901277378038266980760718886034730002089638756146822
      Line 95, in log /nightly/runs/scratch/master/pwm-sim-xcelium/0.pwm_stress_all/latest/run.log

        UVM_ERROR @ 88050096816 ps: (cip_base_vseq.sv:452) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (intr_csrs.size() > 0) Called intr_test vseq without any interrupt register.
        UVM_INFO @ 88050096816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.pwm_stress_all.11627508664941482701040276585114421479567422243514397092732679850638273244829
      Line 86, in log /nightly/runs/scratch/master/pwm-sim-xcelium/1.pwm_stress_all/latest/run.log

        UVM_ERROR @ 31840692430 ps: (cip_base_vseq.sv:452) [uvm_test_top.env.virtual_sequencer.pwm_common_vseq] Check failed (intr_csrs.size() > 0) Called intr_test vseq without any interrupt register.
        UVM_INFO @ 31840692430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 19 more failures.