RV_TIMER Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	50.524m	635.423ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.210s	61.588us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.320s	47.061us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5.090s	1.256ms	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.410s	105.644us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	3.340s	39.580us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.320s	47.061us	20	20	100.00
		rv_timer_csr_aliasing	2.410s	105.644us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	10.087m	322.049ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.228m	687.073ms	49	50	98.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	23.396m	870.797ms	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	23.396m	870.797ms	50	50	100.00
V2	stress	rv_timer_stress_all	42.162m	1.555s	48	50	96.00
V2	intr_test	rv_timer_intr_test	2.350s	33.011us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.690s	112.344us	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.690s	112.344us	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.210s	61.588us	5	5	100.00
		rv_timer_csr_rw	2.320s	47.061us	20	20	100.00
		rv_timer_csr_aliasing	2.410s	105.644us	5	5	100.00
		rv_timer_same_csr_outstanding	2.480s	17.973us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.210s	61.588us	5	5	100.00
		rv_timer_csr_rw	2.320s	47.061us	20	20	100.00
		rv_timer_csr_aliasing	2.410s	105.644us	5	5	100.00
		rv_timer_same_csr_outstanding	2.480s	17.973us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	rv_timer_sec_cm	2.350s	127.008us	5	5	100.00
		rv_timer_tl_intg_err	3.120s	189.970us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.120s	189.970us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	59.280s	28.579ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			581	620	93.71

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.80	100.00	99.36	100.00	--	100.00	100.00	99.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:890) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
- Test rv_timer_stress_all_with_rand_reset has 35 failures.
  - 0.rv_timer_stress_all_with_rand_reset.673461049072715401456827715121740316359862472619949991744484281828605086203
    Line 131, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7314546585 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 7314546585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.rv_timer_stress_all_with_rand_reset.84751023852484495296267332048541703110798373441575096797928729082218027429104
    Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 430767125 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 430767125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 33 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test rv_timer_stress_all has 2 failures.

0.rv_timer_stress_all.44693806147963675184612299811874513817015740486066229778743630070648469480748
Line 92, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.rv_timer_stress_all.73717735781983961607873429605004219721169532110280799429386286919700486099061
Line 97, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/21.rv_timer_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_timer_disabled has 1 failures.

11.rv_timer_disabled.55960644333233135633827085202813362849770696336407733203801946871241924252757
Line 75, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/11.rv_timer_disabled/latest/run.log

  UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:794) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test rv_timer_stress_all_with_rand_reset has 1 failures.
  - 31.rv_timer_stress_all_with_rand_reset.113002120334000367949151935927314282212800476974441200475944020412794547932945
    Line 77, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/31.rv_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1954001160 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1954001160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```