27fc640f8d| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 4.433m | 8.002ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 5.000s | 18.598us | 5 | 5 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 5.000s | 30.085us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 7.000s | 60.098us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 5.000s | 62.555us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 5.000s | 33.308us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 5.000s | 30.085us | 20 | 20 | 100.00 |
| spi_host_csr_aliasing | 5.000s | 62.555us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 5.000s | 25.878us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 5.000s | 20.199us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | performance | spi_host_performance | 38.000s | 96.380us | 50 | 50 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 1.667m | 8.785ms | 50 | 50 | 100.00 |
| spi_host_error_cmd | 38.000s | 20.174us | 50 | 50 | 100.00 | ||
| spi_host_event | 11.067m | 169.308ms | 50 | 50 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 57.000s | 1.082ms | 50 | 50 | 100.00 |
| V2 | speed | spi_host_speed | 57.000s | 1.082ms | 50 | 50 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 57.000s | 1.082ms | 50 | 50 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 3.300m | 9.976ms | 50 | 50 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 38.000s | 144.414us | 50 | 50 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 57.000s | 1.082ms | 50 | 50 | 100.00 |
| V2 | full_cycle | spi_host_speed | 57.000s | 1.082ms | 50 | 50 | 100.00 |
| V2 | duplex | spi_host_smoke | 4.433m | 8.002ms | 49 | 50 | 98.00 |
| V2 | tx_rx_only | spi_host_smoke | 4.433m | 8.002ms | 49 | 50 | 98.00 |
| V2 | stress_all | spi_host_stress_all | 6.567m | 22.619ms | 48 | 50 | 96.00 |
| V2 | spien | spi_host_spien | 1.783m | 11.953ms | 50 | 50 | 100.00 |
| V2 | stall | spi_host_status_stall | 2.200m | 11.975ms | 47 | 50 | 94.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 53.000s | 1.460ms | 50 | 50 | 100.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 1.667m | 8.785ms | 50 | 50 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 38.000s | 23.527us | 50 | 50 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 5.000s | 45.152us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 7.000s | 554.342us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 7.000s | 554.342us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 5.000s | 18.598us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 5.000s | 30.085us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5.000s | 62.555us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 5.000s | 51.722us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 5.000s | 18.598us | 5 | 5 | 100.00 |
| spi_host_csr_rw | 5.000s | 30.085us | 20 | 20 | 100.00 | ||
| spi_host_csr_aliasing | 5.000s | 62.555us | 5 | 5 | 100.00 | ||
| spi_host_same_csr_outstanding | 5.000s | 51.722us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 685 | 690 | 99.28 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 5.000s | 55.343us | 20 | 20 | 100.00 |
| spi_host_sec_cm | 38.000s | 84.859us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 5.000s | 55.343us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 47.667m | 100.003ms | 0 | 10 | 0.00 | |
| TOTAL | 824 | 840 | 98.10 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 96.33 | 96.76 | 93.24 | 98.70 | 94.90 | 88.02 | 100.00 | 97.21 | 91.56 |
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 5 failures:
1.spi_host_upper_range_clkdiv.108979203440633746647115441664330959707608269382396565831493768677031209158913
Line 154, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100003446454 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xac5d8f94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100003446454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.spi_host_upper_range_clkdiv.32801999271967566960886976826751715229294793915511676190906369619631297621238
Line 163, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100004464039 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x8edc1414, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
UVM_INFO @ 100004464039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
6.spi_host_upper_range_clkdiv.73538329742155244705233783943643441283465409712969384716111554147834135682448
Line 133, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002251732 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x21012e94, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 100002251732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.spi_host_upper_range_clkdiv.67927676828841853577879175341721401161710098342316336684235193784390547769857
Line 133, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/8.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100020499517 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0x9af5ba94, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 100020499517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.spi_host_upper_range_clkdiv.61298722462713668845531822689804312870932555468972558211857485999865054480801
Line 210, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
2.spi_host_upper_range_clkdiv.4331990936750115419198721517377095201593208662772141897482199298717704576556
Line 147, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 100002711152 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xe2d8a594, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
UVM_INFO @ 100002711152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
3.spi_host_upper_range_clkdiv.69813832152393829634670988510844599107824116310152640071121299440628276805597
Line 183, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
UVM_FATAL @ 149669911958 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe1eb0a94, Comparison=CompareOpEq, exp_data=0x1, call_count=16)
UVM_INFO @ 149669911958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=89) has 1 failures:
17.spi_host_status_stall.15827391468861802642006885936690953082546414171864254041604559905021353544446
Line 751, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/17.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10778752570 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x5ba1ba54, Comparison=CompareOpEq, exp_data=0x1, call_count=89)
UVM_INFO @ 10778752570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=74) has 1 failures:
21.spi_host_status_stall.40762221559019790003875783718919577909752480098347627774259195822707833189037
Line 669, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10039801590 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x4d4be194, Comparison=CompareOpEq, exp_data=0x1, call_count=74)
UVM_INFO @ 10039801590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=93) has 1 failures:
25.spi_host_status_stall.60494655552306371206262247320418117791538643142368720842074424811681944084315
Line 759, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/25.spi_host_status_stall/latest/run.log
UVM_FATAL @ 10594265263 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xe4c40454, Comparison=CompareOpEq, exp_data=0x1, call_count=93)
UVM_INFO @ 10594265263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
37.spi_host_stress_all.57727523015715149033763263320680507788652431610140099608072365162374918381732
Line 244, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/37.spi_host_stress_all/latest/run.log
UVM_FATAL @ 16151133245 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xffefbe54, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 16151133245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
41.spi_host_stress_all.115420102568818927222746908522650439215569246728077065025177965078756179558127
Line 188, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/41.spi_host_stress_all/latest/run.log
UVM_FATAL @ 22619222955 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x78e95bd4, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 22619222955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=136) has 1 failures:
45.spi_host_smoke.76785501315299300740066054706655196790618517299916379558145362349995570459008
Line 701, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/45.spi_host_smoke/latest/run.log
UVM_FATAL @ 189695301248 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xd5f2f94, Comparison=CompareOpEq, exp_data=0x0, call_count=136)
UVM_INFO @ 189695301248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---