SYSRST_CTRL Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	9.180s	2.115ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	12.590s	2.474ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	9.270s	2.400ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	8.450s	2.513ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	14.050s	6.051ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	9.810s	2.035ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.787m	57.418ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	11.990s	2.580ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	10.230s	2.064ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	9.810s	2.035ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.990s	2.580ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.416m	189.009ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	6.379m	179.927ms	96	100	96.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	11.547m	236.500ms	50	50	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	14.206m	391.834ms	48	50	96.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	12.350s	2.512ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	10.140s	2.156ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	25.837m	657.629ms	49	50	98.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	12.290s	2.613ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	2.455m	1.464s	39	50	78.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	57.020s	39.799ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	14.692m	419.609ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	9.710s	2.014ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	10.620s	2.014ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	10.730s	2.052ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	10.730s	2.052ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	14.050s	6.051ms	5	5	100.00
		sysrst_ctrl_csr_rw	9.810s	2.035ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.990s	2.580ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	41.330s	9.698ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	14.050s	6.051ms	5	5	100.00
		sysrst_ctrl_csr_rw	9.810s	2.035ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.990s	2.580ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	41.330s	9.698ms	20	20	100.00
V2		TOTAL			673	692	97.25
V2S	tl_intg_err	sysrst_ctrl_sec_cm	51.650s	22.014ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	2.144m	44.358ms	18	20	90.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	2.144m	44.358ms	18	20	90.00
V2S		TOTAL			23	25	92.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	22.170s	5.870ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			910	932	97.64

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.06	99.20	98.06	100.00	96.79	99.44	99.42	86.52

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:249) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 11 failures:

Test sysrst_ctrl_ultra_low_pwr has 9 failures.

1.sysrst_ctrl_ultra_low_pwr.103628176761925431312894256782856714158431682553250180225358653557443636381182
Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 617014591058 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 986213508431 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_FATAL @ 996220368773 ps: (cip_base_vseq.sv:573) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred!
  UVM_INFO @ 996220368773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.sysrst_ctrl_ultra_low_pwr.30174101648503451791537682698507986608037318963194298923082853692524794250401
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 5580500600 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 12099107701 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_FATAL @ 22107552815 ps: (cip_base_vseq.sv:573) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] timeout occurred!
  UVM_INFO @ 22107552815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test sysrst_ctrl_edge_detect has 2 failures.

24.sysrst_ctrl_edge_detect.76057944700790223812810470561291630261055063007674738750407811760839068005461
Line 399, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 3981130608 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_FATAL @ 14149770607 ps: (cip_base_vseq.sv:573) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] timeout occurred!
  UVM_INFO @ 14149770607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

39.sysrst_ctrl_edge_detect.4435709998440263572469160339189086741028382592909468653858462075452053031453
Line 391, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest/run.log

  UVM_ERROR @ 5242409947 ps: (cip_base_scoreboard.sv:249) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_FATAL @ 15414619657 ps: (cip_base_vseq.sv:573) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] timeout occurred!
  UVM_INFO @ 15414619657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 2 failures:

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

3.sysrst_ctrl_ultra_low_pwr.57165731517426903780371159870310638311318053377444766667715833178108333812372
Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2436367918 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 40718867918 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 278638867918 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 278651084803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test sysrst_ctrl_stress_all has 1 failures.

25.sysrst_ctrl_stress_all.4580997545381962539736025961248336409165486374533454568121497166330657898905
Line 386, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 11630760422 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 11788260422 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:95) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a L2H transition on lid_open_i
  UVM_INFO @ 14773260422 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 14820557675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (cip_base_vseq.sv:665) [sysrst_ctrl_common_vseq] timeout wait for alert handshake:fatal_fault has 2 failures:
- Test sysrst_ctrl_tl_intg_err has 2 failures.
  - 6.sysrst_ctrl_tl_intg_err.35873902446444260489962781170658734716593477337699777606717915870705616667017
    Line 402, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 20114322948 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] timeout wait for alert handshake:fatal_fault
  UVM_INFO @ 20114322948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.sysrst_ctrl_tl_intg_err.98471421127209985764849974581021890412632199391734927295082014399582810718236
    Line 494, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 44358120471 ps: (cip_base_vseq.sv:665) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] timeout wait for alert handshake:fatal_fault
  UVM_INFO @ 44358120471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 2 failures.

22.sysrst_ctrl_combo_detect_with_pre_cond.96498167711619205006625589136604781044672361649756408188369117556474651595419
Line 389, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 14760868772 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 25046296536 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2c
  UVM_INFO @ 25046316738 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x28
  UVM_INFO @ 27025910718 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 27040868772 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= d

71.sysrst_ctrl_combo_detect_with_pre_cond.77427751249807756173464517040676460237918778677387284322164935390440834416378
Line 458, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 106306031696 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 106306031696 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 106306031696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:184) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_ultra_low_pwr has 1 failures.

5.sysrst_ctrl_ultra_low_pwr.12778110727233863863114662619323984591651735456404662630854274539744656685391
Line 380, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2726061460 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:184) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 2726101999 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.wkup_status reset value: 0x0
  UVM_INFO @ 2726101999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

10.sysrst_ctrl_combo_detect_with_pre_cond.98482181761777147263749286427554313003164301654349764332496057135324159732258
Line 435, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 48425260020 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(3) +/-4
  UVM_INFO @ 58654486865 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x27
  UVM_INFO @ 58654686865 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x12
  UVM_INFO @ 61220686865 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 1
  UVM_INFO @ 61220686865 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 2

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

11.sysrst_ctrl_combo_detect_with_pre_cond.33000176168936264430753187500680538845020329238724685675361087362970188012764
Line 389, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 13448568041 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4
  UVM_ERROR @ 13448568041 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 13448568041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_pin_access_vseq.sv:37) [sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key1_in == rdata_key1_in (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

16.sysrst_ctrl_stress_all_with_rand_reset.51369947929984852980103999545639313216803458992933960574094662231434470735398
Line 432, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12399241027 ps: (sysrst_ctrl_pin_access_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.key1_in == rdata_key1_in (1 [0x1] vs 0 [0x0])
  UVM_ERROR @ 12399241027 ps: (sysrst_ctrl_pin_access_vseq.sv:39) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_pin_access_vseq] Check failed cfg.vif.ec_rst_l_in == rdata_ec_rst_l_in (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 12399241027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 1 failures:
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 36.sysrst_ctrl_ec_pwr_on_rst.25248417913058275930917030416859171547814272462477651529797056489341299601312
    Line 379, in log /nightly/runs/scratch/master/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 2433147293 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 2433147293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```