UART Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	28.370s	10.516ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.130s	57.728us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.270s	16.745us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.310s	255.448us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.490s	127.595us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.860s	100.350us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.270s	16.745us	20	20	100.00
		uart_csr_aliasing	2.490s	127.595us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	7.042m	68.910ms	50	50	100.00
V2	parity	uart_smoke	28.370s	10.516ms	50	50	100.00
		uart_tx_rx	7.042m	68.910ms	50	50	100.00
V2	parity_error	uart_intr	7.276m	191.459ms	50	50	100.00
		uart_rx_parity_err	3.041m	151.050ms	50	50	100.00
V2	watermark	uart_tx_rx	7.042m	68.910ms	50	50	100.00
		uart_intr	7.276m	191.459ms	50	50	100.00
V2	fifo_full	uart_fifo_full	7.465m	155.612ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	4.981m	122.611ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.241m	218.640ms	300	300	100.00
V2	rx_frame_err	uart_intr	7.276m	191.459ms	50	50	100.00
V2	rx_break_err	uart_intr	7.276m	191.459ms	50	50	100.00
V2	rx_timeout	uart_intr	7.276m	191.459ms	50	50	100.00
V2	perf	uart_perf	19.097m	25.418ms	49	50	98.00
V2	sys_loopback	uart_loopback	54.230s	15.222ms	50	50	100.00
V2	line_loopback	uart_loopback	54.230s	15.222ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	6.554m	90.853ms	49	50	98.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.161m	34.259ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	26.300s	6.957ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.279m	7.732ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	22.427m	149.102ms	50	50	100.00
V2	stress_all	uart_stress_all	26.625m	227.813ms	50	50	100.00
V2	alert_test	uart_alert_test	2.250s	67.692us	50	50	100.00
V2	intr_test	uart_intr_test	2.250s	135.310us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.490s	378.337us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.490s	378.337us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.130s	57.728us	5	5	100.00
		uart_csr_rw	2.270s	16.745us	20	20	100.00
		uart_csr_aliasing	2.490s	127.595us	5	5	100.00
		uart_same_csr_outstanding	2.290s	260.349us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.130s	57.728us	5	5	100.00
		uart_csr_rw	2.270s	16.745us	20	20	100.00
		uart_csr_aliasing	2.490s	127.595us	5	5	100.00
		uart_same_csr_outstanding	2.290s	260.349us	20	20	100.00
V2		TOTAL			1088	1090	99.82
V2S	tl_intg_err	uart_sec_cm	2.510s	58.526us	5	5	100.00
		uart_tl_intg_err	2.880s	152.527us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.880s	152.527us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.117m	24.832ms	96	100	96.00
V3		TOTAL			96	100	96.00
		TOTAL			1314	1320	99.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.77	99.18	98.25	91.55	--	98.14	100.00	99.53

Failure Buckets

UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 3 failures:

Test uart_stress_all_with_rand_reset has 2 failures.

9.uart_stress_all_with_rand_reset.66632031905442830037062921181144229321349967045126030381520630707089383726633
Line 176, in log /nightly/runs/scratch/master/uart-sim-vcs/9.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3271896836 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 3278480701 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 8/10
  UVM_INFO @ 3278563173 ps: (cip_base_vseq.sv:818) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 8/10

49.uart_stress_all_with_rand_reset.73628608101899998414496038527377144602562724977022023559806073453150459152277
Line 107, in log /nightly/runs/scratch/master/uart-sim-vcs/49.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1495193459 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_INFO @ 1548550175 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/156
  UVM_INFO @ 1560050083 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_rx_parity_err_vseq] finished run 1/6
  UVM_INFO @ 1691870457 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/156
  UVM_INFO @ 1728852304 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 4/156

Test uart_perf has 1 failures.

38.uart_perf.93587082371042864718243255221672559031400627322613984294385767881661293052849
Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/38.uart_perf/latest/run.log

  UVM_ERROR @   3234186 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
  UVM_ERROR @   3234186 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
  UVM_INFO @ 1724426375 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 1/6
  UVM_INFO @ 1965254200 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 2/6
  UVM_INFO @ 1965754186 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_perf_vseq] finished run 3/6

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test uart_noise_filter has 1 failures.
  - 29.uart_noise_filter.46510183137111156594339775684943745138072746254250718923387756800628509042115
    Line 80, in log /nightly/runs/scratch/master/uart-sim-vcs/29.uart_noise_filter/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_vseq.sv:794) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

87.uart_stress_all_with_rand_reset.64398213916201202042869207250193353342697239139960675072795306220990118557
Line 140, in log /nightly/runs/scratch/master/uart-sim-vcs/87.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2267775576 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2267775576 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 5/5
  UVM_INFO @ 2267855576 ps: (cip_base_vseq.sv:818) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Stress w/ reset is done for run 5/5

UVM_ERROR (cip_base_vseq.sv:890) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

Test uart_stress_all_with_rand_reset has 1 failures.

94.uart_stress_all_with_rand_reset.32668048340650212291287490182189924513071687908061282743116091516020739987806
Line 93, in log /nightly/runs/scratch/master/uart-sim-vcs/94.uart_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 444175027 ps: (cip_base_vseq.sv:890) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 444176137 ps: (cip_base_vseq.sv:794) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 444176137 ps: (cip_base_vseq.sv:798) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 444185444 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/2