CHIP Simulation Results

Sunday March 23 2025 00:10:17 UTC

GitHub Revision: `27fc640f8d`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	1.480m		0	3	0.00
		chip_sw_example_rom	1.347m		0	3	0.00
		chip_sw_example_manufacturer	1.263m		0	3	0.00
		chip_sw_example_concurrency	1.229m		0	3	0.00
V1	csr_hw_reset	chip_csr_hw_reset	7.242m	6.254ms	5	5	100.00
V1	csr_rw	chip_csr_rw	10.745m	6.072ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.089h	58.283ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	1.521h	39.152ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	7.879m	7.332ms	3	20	15.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	1.521h	39.152ms	5	5	100.00
		chip_csr_rw	10.745m	6.072ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	12.040s	249.568us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	25.354s		0	3	0.00
V1	chip_sw_gpio_in	chip_sw_gpio	25.354s		0	3	0.00
V1	chip_sw_gpio_irq	chip_sw_gpio	25.354s		0	3	0.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.010m		0	5	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.010m		0	5	0.00
		chip_sw_uart_tx_rx_idx1	58.563s		0	5	0.00
		chip_sw_uart_tx_rx_idx2	57.546s		0	5	0.00
		chip_sw_uart_tx_rx_idx3	54.528s		0	5	0.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	15.928s		0	20	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	25.512s		0	5	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	25.528s		0	5	0.00
V1		TOTAL			138	220	62.73
V2	chip_pin_mux	chip_padctrl_attributes	4.073m	5.049ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.073m	5.049ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	1.111m		0	3	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	1.111m		0	3	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	1.094m		0	3	0.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	45.994s		0	5	0.00
		chip_tap_straps_testunlock0	25.216s		0	5	0.00
		chip_tap_straps_rma	40.035s		0	5	0.00
		chip_tap_straps_prod	1.090s		0	5	0.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	1.077m		0	3	0.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	1.077m		0	3	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	1.111m		0	6	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	1.111m		0	6	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	1.023s		0	3	0.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	40.039s		0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	18.354s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	18.368s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.022s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.064s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	1.070s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.024s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	40.852s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.682s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	1.022s		0	3	0.00
		chip_sw_clkmgr_jitter	1.022s		0	3	0.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib			0	1	0.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	15.813s		0	5	0.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	16.000s		0	3	0.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	1.040s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	16.000s		0	3	0.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	41.953s		0	3	0.00
		chip_sw_aes_smoketest	1.022s		0	3	0.00
		chip_sw_aon_timer_smoketest	1.070s		0	3	0.00
		chip_sw_clkmgr_smoketest	1.023s		0	3	0.00
		chip_sw_csrng_smoketest	1.040s		0	3	0.00
		chip_sw_entropy_src_smoketest	35.638s		0	3	0.00
		chip_sw_gpio_smoketest	1.006s		0	3	0.00
		chip_sw_hmac_smoketest	15.605s		0	3	0.00
		chip_sw_kmac_smoketest	15.661s		0	3	0.00
		chip_sw_otbn_smoketest	16.018s		0	3	0.00
		chip_sw_pwrmgr_smoketest	1.068s		0	3	0.00
		chip_sw_pwrmgr_usbdev_smoketest	15.522s		0	3	0.00
		chip_sw_rv_plic_smoketest	15.676s		0	3	0.00
		chip_sw_rv_timer_smoketest	1.023s		0	3	0.00
		chip_sw_rstmgr_smoketest	26.650s		0	3	0.00
		chip_sw_sram_ctrl_smoketest	1.008s		0	3	0.00
		chip_sw_uart_smoketest	1.042s		0	3	0.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	15.606s		0	3	0.00
V2	chip_sw_rom_functests	rom_keymgr_functest	1.036s		0	3	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	51.465s		0	3	0.00
V2	chip_sw_secure_boot	rom_e2e_smoke	1.071s		0	3	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	15.732s		0	3	0.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	39.856s		0	3	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	38.862s		0	3	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	32.915s		0	3	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	15.320s		0	3	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	4.203m	3.640ms	3	30	10.00
V2	tl_d_illegal_access	chip_tl_errors	4.203m	3.640ms	3	30	10.00
V2	tl_d_outstanding_access	chip_csr_aliasing	1.521h	39.152ms	5	5	100.00
		chip_same_csr_outstanding	59.617m	30.113ms	20	20	100.00
		chip_csr_hw_reset	7.242m	6.254ms	5	5	100.00
		chip_csr_rw	10.745m	6.072ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	1.521h	39.152ms	5	5	100.00
		chip_same_csr_outstanding	59.617m	30.113ms	20	20	100.00
		chip_csr_hw_reset	7.242m	6.254ms	5	5	100.00
		chip_csr_rw	10.745m	6.072ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.204m	2.553ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.630s	59.857us	100	100	100.00
		xbar_smoke_large_delays	2.118m	11.527ms	100	100	100.00
		xbar_smoke_slow_rsp	1.825m	6.431ms	100	100	100.00
		xbar_random_zero_delays	53.650s	629.858us	100	100	100.00
		xbar_random_large_delays	7.737m	58.514ms	100	100	100.00
		xbar_random_slow_rsp	8.176m	36.230ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	58.680s	1.343ms	100	100	100.00
		xbar_error_and_unmapped_addr	48.770s	1.281ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.249m	2.246ms	100	100	100.00
		xbar_error_and_unmapped_addr	48.770s	1.281ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.834m	3.644ms	100	100	100.00
		xbar_access_same_device_slow_rsp	14.710m	85.426ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.000m	1.987ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	8.245m	18.260ms	100	100	100.00
		xbar_stress_all_with_error	8.213m	19.302ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	11.847m	15.497ms	100	100	100.00
		xbar_stress_all_with_reset_error	9.999m	21.806ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	1.071s		0	3	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.023s		0	3	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	1.022s		0	3	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end			0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma			0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end			0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma			0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1.041s		0	3	0.00
		rom_e2e_asm_init_dev	1.022s		0	3	0.00
		rom_e2e_asm_init_prod	32.511s		0	3	0.00
		rom_e2e_asm_init_prod_end	1.023s		0	3	0.00
		rom_e2e_asm_init_rma	15.647s		0	3	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	15.632s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	1.023s		0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	1.023s		0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	15.629s		0	3	0.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	15.634s		0	3	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	15.634s		0	3	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	1.023s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.064s		0	3	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	1.024s		0	3	0.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	1.023s		0	3	0.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	1.040s		0	3	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	59.712s		0	3	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	39.954s		0	3	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	1.178m		0	100	0.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	54.031s		0	3	0.00
		chip_plic_all_irqs_10	27.815s		0	3	0.00
		chip_plic_all_irqs_20	15.671s		0	3	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	1.023s		0	3	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	25.634s		0	3	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	15.558s		0	3	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	41.384s		0	90	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	1.024s		0	3	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	1.023s		0	3	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	1.024s		0	3	0.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	48.138s		0	3	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	1.023s		0	3	0.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	1.040s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	1.068s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	1.040s		0	3	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	1.040s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	1.040s		0	3	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	1.068s		0	5	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	1.024s		0	3	0.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	1.022s		0	3	0.00
		chip_sw_aes_idle	1.023s		0	3	0.00
		chip_sw_hmac_enc_idle	1.093s		0	3	0.00
		chip_sw_kmac_idle	31.620s		0	3	0.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	49.124s		0	3	0.00
		chip_sw_clkmgr_off_hmac_trans	1.070s		0	3	0.00
		chip_sw_clkmgr_off_kmac_trans	1.023s		0	3	0.00
		chip_sw_clkmgr_off_otbn_trans	1.040s		0	3	0.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	1.023s		0	3	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	1.024s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	1.023s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.071s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.023s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	1.040s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.668s		0	3	0.00
		chip_sw_ast_clk_outputs	1.023s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	32.214s		0	3	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.071s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.023s		0	3	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	18.354s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	18.368s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.022s		0	3	0.00
		chip_sw_aes_enc_jitter_en	1.064s		0	3	0.00
		chip_sw_edn_entropy_reqs_jitter	1.070s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.024s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	40.852s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.682s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	1.022s		0	3	0.00
		chip_sw_clkmgr_jitter	1.022s		0	3	0.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	1.062s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	32.387s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	26.606s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.008s		0	3	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	1.041s		0	3	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.023s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	30.260s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	1.023s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	1.023s		0	3	0.00
		chip_sw_flash_init_reduced_freq	1.022s		0	3	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	35.661s		0	3	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	1.023s		0	3	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	1.009s		0	3	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	1.023s		0	3	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	1.178m		0	100	0.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	1.023s		0	3	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	1.070s		0	3	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	15.634s		0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	1.024s		0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	1.024s		0	3	0.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	40.092s		0	10	0.00
		chip_sw_entropy_src_ast_rng_req	32.518s		0	3	0.00
		chip_sw_edn_entropy_reqs	15.712s		0	3	0.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	32.518s		0	3	0.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	1.070s		0	3	0.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	1.023s		0	3	0.00
V2	chip_sw_flash_init	chip_sw_flash_init	18.372s		0	3	0.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	1.040s		0	3	0.00
		chip_sw_flash_ctrl_access_jitter_en	18.368s		0	3	0.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	18.344s		0	3	0.00
		chip_sw_flash_ctrl_ops_jitter_en	18.354s		0	3	0.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.040s		0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	18.372s		0	3	0.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	26.580s		0	3	0.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	1.046s		0	3	0.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	18.363s		0	3	0.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.040s		0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	18.363s		0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	18.363s		0	3	0.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	18.363s		0	3	0.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	18.363s		0	3	0.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	1.178m		0	100	0.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	7.644m	15.182ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	1.023s		0	3	0.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	25.009s		0	3	0.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	25.009s		0	3	0.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	1.024s		0	3	0.00
		chip_sw_hmac_enc_jitter_en	1.024s		0	3	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	1.093s		0	3	0.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	1.041s		0	3	0.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	39.755s		0	3	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	22.532s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx1	1.022s		0	3	0.00
		chip_sw_i2c_host_tx_rx_idx2	25.178s		0	3	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	18.301s		0	3	0.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	1.046s		0	3	0.00
		chip_sw_keymgr_key_derivation_jitter_en	40.852s		0	3	0.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	1.008s		0	3	0.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	1.040s		0	3	0.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.023s		0	3	0.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	1.135s		0	3	0.00
		chip_sw_kmac_mode_kmac	1.022s		0	3	0.00
		chip_sw_kmac_mode_kmac_jitter_en	39.682s		0	3	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	1.046s		0	3	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	26.676s		0	15	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	1.022s		0	3	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	18.371s		0	3	0.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	31.620s		0	3	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	39.954s		0	3	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	45.994s		0	5	0.00
		chip_tap_straps_rma	40.035s		0	5	0.00
		chip_tap_straps_prod	1.090s		0	5	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	39.818s		0	3	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	26.676s		0	15	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	26.676s		0	15	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	26.676s		0	15	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	15.646s		0	3	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	18.363s		0	3	0.00
		chip_sw_flash_rma_unlocked	1.040s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	18.387s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	18.395s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	47.004s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.410s		0	3	0.00
		chip_sw_lc_ctrl_transition	26.676s		0	15	0.00
		chip_sw_keymgr_key_derivation	1.046s		0	3	0.00
		chip_sw_rom_ctrl_integrity_check	15.603s		0	3	0.00
		chip_sw_sram_ctrl_execution_main	1.069s		0	3	0.00
		chip_prim_tl_access	7.644m	15.182ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	32.214s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	1.024s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	1.023s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	1.071s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	1.023s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	1.040s		0	3	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	15.668s		0	3	0.00
		chip_tap_straps_dev	45.994s		0	5	0.00
		chip_tap_straps_rma	40.035s		0	5	0.00
		chip_tap_straps_prod	1.090s		0	5	0.00
		chip_rv_dm_lc_disabled	9.024m	15.659ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap			0	1	0.00
		chip_sw_lc_ctrl_raw_to_scrap			0	1	0.00
		chip_sw_lc_ctrl_test_locked0_to_scrap			0	1	0.00
		chip_sw_lc_ctrl_rand_to_scrap	15.818s		0	3	0.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	25.076s		0	3	0.00
		chip_rv_dm_lc_disabled	9.024m	15.659ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.008s		0	3	0.00
		chip_sw_lc_walkthrough_prod	1.006s		0	3	0.00
		chip_sw_lc_walkthrough_prodend	1.006s		0	3	0.00
		chip_sw_lc_walkthrough_rma	1.072s		0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	25.076s		0	3	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.072s		0	3	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	25.395s		0	3	0.00
		rom_volatile_raw_unlock	15.647s		0	3	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.909s		0	3	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.022s		0	3	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	1.022s		0	3	0.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	1.022s		0	3	0.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	1.022s		0	3	0.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	1.023s		0	3	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	26.676s		0	15	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	18.372s		0	3	0.00
		chip_sw_otbn_mem_scramble	1.023s		0	3	0.00
		chip_sw_keymgr_key_derivation	1.046s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	38.797s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	25.546s		0	3	0.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	18.372s		0	3	0.00
		chip_sw_otbn_mem_scramble	1.023s		0	3	0.00
		chip_sw_keymgr_key_derivation	1.046s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access	38.797s		0	3	0.00
		chip_sw_rv_core_ibex_icache_invalidate	25.546s		0	3	0.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	26.676s		0	15	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	1.210m		0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	39.818s		0	3	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	18.387s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_dev	18.395s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_prod	47.004s		0	3	0.00
		chip_sw_otp_ctrl_lc_signals_rma	18.410s		0	3	0.00
		chip_sw_lc_ctrl_transition	26.676s		0	15	0.00
		chip_prim_tl_access	7.644m	15.182ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	7.644m	15.182ms	3	3	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	18.434s		0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	40.011s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	25.058s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	1.024s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	1.023s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	38.650s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	1.073s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	15.567s		0	3	0.00
		chip_sw_aon_timer_wdog_bite_reset	1.040s		0	3	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	1.022s		0	3	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	15.582s		0	3	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	40.011s		0	3	0.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	1.022s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.023s		0	3	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	1.023s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	1.071s		0	3	0.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	1.069s		0	3	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	1.040s		0	3	0.00
		chip_sw_pwrmgr_all_reset_reqs	1.009s		0	3	0.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	1.090s		0	3	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	1.023s		0	3	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	1.178m		0	100	0.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	15.603s		0	3	0.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	15.603s		0	3	0.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	1.009s		0	3	0.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	1.069s		0	3	0.00
		chip_sw_pwrmgr_wdog_reset	15.582s		0	3	0.00
		chip_sw_pwrmgr_smoketest	1.068s		0	3	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	1.111s		0	3	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	1.022s		0	3	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	1.024s		0	3	0.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	25.634s		0	3	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	1.023s		0	3	0.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	1.178m		0	100	0.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	1.024s		0	3	0.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	1.006s		0	3	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	1.023s		0	3	0.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	1.093s		0	3	0.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	25.546s		0	3	0.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	1.022s		0	3	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	1.022s		0	3	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	6.504m	8.911ms	1	3	33.33
V2	chip_jtag_mem_access	chip_jtag_mem_access	10.555m	13.632ms	1	3	33.33
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	1.111s		0	3	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	15.629s		0	3	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	15.632s		0	3	0.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	40.035s		0	5	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	9.024m	15.659ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	54.031s		0	3	0.00
		chip_plic_all_irqs_10	27.815s		0	3	0.00
		chip_plic_all_irqs_20	15.671s		0	3	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	1.024s		0	3	0.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	1.023s		0	3	0.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	1.071s		0	3	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	54.370s		0	3	0.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	18.325s		0	3	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	18.313s		0	3	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	25.294s		0	3	0.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	38.797s		0	3	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	1.022s		0	3	0.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	25.148s		0	3	0.00
		chip_sw_sleep_sram_ret_contents_scramble	1.008s		0	3	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	1.069s		0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	1.178m		0	100	0.00
		chip_sw_data_integrity_escalation	1.111m		0	6	0.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	1.040s		0	3	0.00
		chip_sw_sysrst_ctrl_reset	24.761s		0	3	0.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	1.073s		0	3	0.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	25.876s		0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	35.638s		0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	24.761s		0	3	0.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	24.761s		0	3	0.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.070s		0	3	0.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.070s		0	3	0.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	1.042s		0	3	0.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	15.634s		0	3	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	49.450s		0	1	0.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	38.374s		0	1	0.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	38.380s		0	1	0.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	36.367s		0	1	0.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	32.360s		0	1	0.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	29.347s		0	1	0.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	47.438s		0	1	0.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	27.333s		0	1	0.00
V2		TOTAL			1741	2657	65.53
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	31.382s		0	3	0.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	15.615s		0	3	0.00
V2S		TOTAL			0	6	0.00
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	1.069s		0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0			0	1	0.00
		rom_e2e_jtag_debug_dev			0	1	0.00
		rom_e2e_jtag_debug_rma			0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0			0	1	0.00
		rom_e2e_jtag_inject_dev			0	1	0.00
		rom_e2e_jtag_inject_rma			0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	15.659s		0	3	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	1.023s		0	3	0.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	1.022s		0	3	0.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	15.640s		0	3	0.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	25.004s		0	3	0.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	37.823s		0	3	0.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	1.023s		0	3	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	18.418s		0	3	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.426s		0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	1.023s		0	3	0.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	25.127s		0	3	0.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	1.009s		0	3	0.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0			0	1	0.00
		rom_e2e_jtag_debug_dev			0	1	0.00
		rom_e2e_jtag_debug_rma			0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	38.778s		0	3	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	1.178m		0	100	0.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	25.065s		0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	25.065s		0	3	0.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	1.006s		0	3	0.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	1.010m		0	5	0.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	28.338s		0	1	0.00
V3		TOTAL			0	51	0.00
	Unmapped tests	chip_sival_flash_info_access	1.212m		0	3	0.00
		chip_sw_rstmgr_rst_cnsty_escalation	1.145m		0	3	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	32.379s		0	3	0.00
		chip_sw_otp_ctrl_descrambling	18.455s		0	3	0.00
		chip_sw_pwrmgr_lowpower_cancel	1.023s		0	3	0.00
		chip_sw_pwrmgr_sleep_wake_5_bug	1.024s		0	3	0.00
		chip_sw_flash_ctrl_write_clear	25.049s		0	3	0.00
		TOTAL			1879	2955	63.59

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
84.94	85.53	84.66	67.19	--	85.63	87.93	98.68

Failure Buckets

Job returned non-zero exit code has 805 failures:

Test chip_sw_example_flash has 3 failures.

0.chip_sw_example_flash.83728119419495604651371988112647103299455952919470347621335697654523521404428
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_flash/latest/run.log

      at com.google.devtools.build.lib.skyframe.BuildDriverFunction.compute(BuildDriverFunction.java:240)
      at com.google.devtools.build.skyframe.AbstractParallelEvaluator$Evaluate.run(AbstractParallelEvaluator.java:467)
      at com.google.devtools.build.lib.concurrent.AbstractQueueVisitor$WrappedRunnable.run(AbstractQueueVisitor.java:435)
      at java.base/java.util.concurrent.ForkJoinTask$RunnableExecuteAction.exec(Unknown Source)
      at java.base/java.util.concurrent.ForkJoinTask.doExec(Unknown Source)
      at java.base/java.util.concurrent.ForkJoinPool$WorkQueue.topLevelExec(Unknown Source)
      at java.base/java.util.concurrent.ForkJoinPool.scan(Unknown Source)
      at java.base/java.util.concurrent.ForkJoinPool.runWorker(Unknown Source)
      at java.base/java.util.concurrent.ForkJoinWorkerThread.run(Unknown Source)
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 33

1.chip_sw_example_flash.29801206018104186277995195454585852700790762675524331960045995895710375520580
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest/run.log

        --quiet --img-seed 29801206018104186277995195454585852700790762675524331960045995895710375520580 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson && /nightly/runs/opentitan/util/design/gen-otp-img.py \
        --img-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 29801206018104186277995195454585852700790762675524331960045995895710375520580 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_flash/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1373153604 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.1373153604' seed=29801206018104186277995195454585852700790762675524331960045995895710375520580 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='' sw_images='//sw/device/tests:example_test_from_flash:1:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 1 more failures.

Test chip_sw_example_rom has 3 failures.

0.chip_sw_example_rom.85023000697818145419615967968953900263949076194305121513434865029934890608911
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log

              done; \
          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_test_from_rom_sim_dv".
  Building "//sw/device/tests:example_test_from_rom_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=85023000697818145419615967968953900263949076194305121513434865029934890608911 //sw/device/tests:example_test_from_rom_sim_dv
  Another command (pid=3270075) is running. Waiting for it to complete on the server (server_pid=2725756)...
  bazel is crashing: Crashed: (java.lang.OutOfMemoryError) unable to create native thread: possibly out of memory or process/resource limits reached
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

1.chip_sw_example_rom.552098905354318682073996038079104030915166995688309125406539532020334755113
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest/run.log

        --quiet --img-seed 552098905354318682073996038079104030915166995688309125406539532020334755113 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson && /nightly/runs/opentitan/util/design/gen-otp-img.py \
        --img-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 552098905354318682073996038079104030915166995688309125406539532020334755113 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_rom/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1387822377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.1387822377' seed=552098905354318682073996038079104030915166995688309125406539532020334755113 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='' sw_images=//sw/device/tests:example_test_from_rom:0:test_in_rom:new_rules uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 1 more failures.

Test chip_sw_example_manufacturer has 3 failures.

0.chip_sw_example_manufacturer.74951040276918433991992015136423688391122094171966185525410718290288641524268
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

              done; \
          fi; \
      fi; \
  done;
  Building SW image "@manufacturer_test_hooks//:example_test_sim_dv".
  Building "@manufacturer_test_hooks//:example_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=74951040276918433991992015136423688391122094171966185525410718290288641524268 @manufacturer_test_hooks//:example_test_sim_dv
  Another command (pid=3270075) is running. Waiting for it to complete on the server (server_pid=2725756)...
  bazel is crashing: Crashed: (java.lang.OutOfMemoryError) unable to create native thread: possibly out of memory or process/resource limits reached
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

1.chip_sw_example_manufacturer.60891384827573817313736396752050367679325880671685917002707668283182746192799
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/run.log

        --quiet --img-seed 60891384827573817313736396752050367679325880671685917002707668283182746192799 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson && /nightly/runs/opentitan/util/design/gen-otp-img.py \
        --img-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 60891384827573817313736396752050367679325880671685917002707668283182746192799 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_manufacturer/latest run_opts='+sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3630189471 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.3630189471' seed=60891384827573817313736396752050367679325880671685917002707668283182746192799 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='' sw_images='@manufacturer_test_hooks//:example_test:1:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 1 more failures.

Test chip_sw_example_concurrency has 3 failures.

0.chip_sw_example_concurrency.24718940073161624057716568965634198176252648218515110122913244687335254402023
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_example_concurrency/latest/run.log

              done; \
          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:example_concurrency_test_sim_dv".
  Building "//sw/device/tests:example_concurrency_test_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=24718940073161624057716568965634198176252648218515110122913244687335254402023 //sw/device/tests:example_concurrency_test_sim_dv
  Another command (pid=3270075) is running. Waiting for it to complete on the server (server_pid=2725756)...
  bazel is crashing: Crashed: (java.lang.OutOfMemoryError) unable to create native thread: possibly out of memory or process/resource limits reached
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

1.chip_sw_example_concurrency.29877811255406541740764242129567825232244011361734981967986372722231124478728
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest/run.log

        --quiet --img-seed 29877811255406541740764242129567825232244011361734981967986372722231124478728 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson && /nightly/runs/opentitan/util/design/gen-otp-img.py \
        --img-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 29877811255406541740764242129567825232244011361734981967986372722231124478728 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sw_example_concurrency/latest run_opts='+sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=77122312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.77122312' seed=29877811255406541740764242129567825232244011361734981967986372722231124478728 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='' sw_images='//sw/device/tests:example_concurrency_test:1:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 1 more failures.

Test chip_sival_flash_info_access has 3 failures.

0.chip_sival_flash_info_access.56434796143285271411432022927532257753850008769575348954485017415352432910751
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sival_flash_info_access/latest/run.log

              done; \
          fi; \
      fi; \
  done;
  Building SW image "//sw/device/tests:flash_ctrl_info_access_lc_sim_dv".
  Building "//sw/device/tests:flash_ctrl_info_access_lc_sim_dv" on network connected machine.
  Building with command: ./bazelisk.sh build  --define DISABLE_VERILATOR_BUILD=true --//util/design/data:img_seed=56434796143285271411432022927532257753850008769575348954485017415352432910751 //sw/device/tests:flash_ctrl_info_access_lc_sim_dv
  Another command (pid=3270075) is running. Waiting for it to complete on the server (server_pid=2725756)...
  bazel is crashing: Crashed: (java.lang.OutOfMemoryError) unable to create native thread: possibly out of memory or process/resource limits reached
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 36

1.chip_sival_flash_info_access.48431045848133946952062815080082835356767953238455844017320148467067007241403
Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest/run.log

        --quiet --img-seed 48431045848133946952062815080082835356767953238455844017320148467067007241403 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson && /nightly/runs/opentitan/util/design/gen-otp-img.py \
        --img-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_rma.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_creator_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_owner_sw_cfg.hjson \
        --add-cfg /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_img_hw_cfg.hjson \
        --out /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest/otp_ctrl_img_rma.vmem \
        --quiet --img-seed 48431045848133946952062815080082835356767953238455844017320148467067007241403 --mmap-def /nightly/runs/opentitan/hw/top_earlgrey/data/otp/otp_ctrl_mmap.hjson' proj_root=/nightly/runs/opentitan run_cmd=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/default/simv run_dir=/nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_sival_flash_info_access/latest run_opts='+use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/runs/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1869581499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1869581499' seed=48431045848133946952062815080082835356767953238455844017320148467067007241403 sw_build_cmd=bazel sw_build_device=sim_dv sw_build_opts='' sw_images='//sw/device/tests:flash_ctrl_info_access_lc:1:new_rules //sw/device/lib/testing/test_rom:test_rom:0' uvm_test=chip_base_test uvm_test_seq=chip_sw_base_vseq

  make: /bin/bash: Operation not permitted
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 127

... and 1 more failures.

... and 251 more tests.

Job timed out after * minutes has 227 failures:
- Test chip_sw_i2c_host_tx_rx_idx1 has 1 failures.
  - 0.chip_sw_i2c_host_tx_rx_idx1.52529581409582020328802406032925368076915331641696441080991972451960628973983
    Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_i2c_host_tx_rx_idx1/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_spi_device_pinmux_sleep_retention has 1 failures.
  - 0.chip_sw_spi_device_pinmux_sleep_retention.106385386380450831068464127727342884161573286635274756739424276526069249176595
    Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pinmux_sleep_retention/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_spi_device_pass_through has 1 failures.
  - 0.chip_sw_spi_device_pass_through.53632879554806151376800953170500987341830251010974831373297042119377490162353
    Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_flash_ctrl_access has 1 failures.
  - 0.chip_sw_flash_ctrl_access.33011614748788060140778442315567029407362063038825409050044793494250290915473
    Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_access/latest/run.log
```
  Job timed out after 60 minutes
```
- Test chip_sw_flash_ctrl_idle_low_power has 1 failures.
  - 0.chip_sw_flash_ctrl_idle_low_power.21749982000074837618040525525442107294268815579992742649495665984882647393021
    Log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_idle_low_power/latest/run.log
```
  Job timed out after 60 minutes
```
- ... and 222 more tests.

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32075) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_csr_mem_rw_with_rand_reset has 2 failures.

13.chip_csr_mem_rw_with_rand_reset.87850717853593268670241789123321590414993715768379479381261913967545116819133
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2479.957164 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32075) { a_addr: 'h10740  a_data: 'ha34bb4b7  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h1b16e  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2479.957164 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.chip_csr_mem_rw_with_rand_reset.95062164109985293597642954527906065971025569056607533064163763745238782293499
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1927.444400 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32075) { a_addr: 'h10378  a_data: 'he5884996  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h4  a_user: 'h18a9f  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1927.444400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35585) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.8173580259126511477692470926366373233832076053167193637243698378879955442896
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2754.734700 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35585) { a_addr: 'h10480  a_data: 'h9e9137c0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h31  a_opcode: 'h4  a_user: 'h1a53a  d_param: 'h0  d_source: 'h31  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2754.734700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216951) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.13096826250932678190187099302428252344434433865575263133422375021058641346735
Line 246, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 6518.191088 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216951) { a_addr: 'h10600  a_data: 'hb447e47e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h29  a_opcode: 'h4  a_user: 'h19ec9  d_param: 'h0  d_source: 'h29  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 6518.191088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32999) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

1.chip_tl_errors.45079993610287538820939343643027520897671263032900030957794764551605920905785
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2386.057444 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32999) { a_addr: 'h10488  a_data: 'h8c774324  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h1b1d2  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2386.057444 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@214205) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

1.chip_csr_mem_rw_with_rand_reset.83103600755794669307947441824574309514297281091134848578845094091944298234540
Line 246, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5865.566728 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@214205) { a_addr: 'h1041c  a_data: 'h8323e89d  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h18  a_opcode: 'h4  a_user: 'h1a917  d_param: 'h0  d_source: 'h18  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5865.566728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216069) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

2.chip_csr_mem_rw_with_rand_reset.75199078153046739996439526225941424310975283872785100320639002995641748386665
Line 246, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/2.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 5284.791131 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@216069) { a_addr: 'h10548  a_data: 'h9cca34c1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h4  a_user: 'h1aeca  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5284.791131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32515) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

4.chip_tl_errors.11650444529183287265490095413378531863713198224054055766826446608442474282335
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2486.136596 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32515) { a_addr: 'h10520  a_data: 'hbe22f8ab  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h18a6e  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2486.136596 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@215835) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

4.chip_csr_mem_rw_with_rand_reset.18203502096670931826301637059074400203110852687997835836354871417872510941106
Line 246, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/4.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 4456.184249 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@215835) { a_addr: 'h105a0  a_data: 'hc2ba839c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h1bad3  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4456.184249 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32051) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

5.chip_tl_errors.15971760846292031884082428370547422753964071007854794413167431851117403736208
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2327.153496 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32051) { a_addr: 'h10790  a_data: 'hc0107fff  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h13  a_opcode: 'h4  a_user: 'h18de8  d_param: 'h0  d_source: 'h13  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2327.153496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32279) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

5.chip_csr_mem_rw_with_rand_reset.115546979137719238410493600759227638233745684172411573804212896300654179026268
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/5.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2210.201740 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32279) { a_addr: 'h10714  a_data: 'hf296099a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3f  a_opcode: 'h4  a_user: 'h1b1ba  d_param: 'h0  d_source: 'h3f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2210.201740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37663) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

6.chip_tl_errors.47880245465351553947349159045887556387792185080773802532792607254830326978896
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2584.678972 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37663) { a_addr: 'h1062c  a_data: 'h5ebe050e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h15  a_opcode: 'h4  a_user: 'h19e5b  d_param: 'h0  d_source: 'h15  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2584.678972 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

6.chip_csr_mem_rw_with_rand_reset.95275623448172391620632232602764163558590148944519479558333791618741165697768
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/6.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1869.464468 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31937) { a_addr: 'h10478  a_data: 'h821015a6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'he  a_opcode: 'h4  a_user: 'h1959c  d_param: 'h0  d_source: 'he  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1869.464468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34293) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

7.chip_tl_errors.57236280792325917776438295442690848769554977422824555188624359179600368190136
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2271.401980 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34293) { a_addr: 'h105fc  a_data: 'h83692f45  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2d  a_opcode: 'h4  a_user: 'h1aed9  d_param: 'h0  d_source: 'h2d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2271.401980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@218701) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

7.chip_csr_mem_rw_with_rand_reset.39280851082761979015249565817799301580953465437969564760669129282049459006703
Line 246, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/7.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 7332.325980 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@218701) { a_addr: 'h10404  a_data: 'h638ecbb1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h19955  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 7332.325980 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36751) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

8.chip_tl_errors.7888405699782754034496465622239513232173317441726002687970413353684319128266
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/8.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2621.296904 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36751) { a_addr: 'h105cc  a_data: 'hb8d3d4f0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h4  a_user: 'h192f4  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2621.296904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32901) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

9.chip_tl_errors.53257347808110991287263276787547495573869080006783883807431884251430406383469
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2381.574392 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32901) { a_addr: 'h107a0  a_data: 'h5ea06c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h1b1c8  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2381.574392 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32025) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

9.chip_csr_mem_rw_with_rand_reset.48891178910415695172961180225263418796963719420673759989312568146544588654601
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/9.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2326.781776 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32025) { a_addr: 'h10634  a_data: 'h5596b5ea  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h1ae5b  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2326.781776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34449) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

10.chip_tl_errors.39057798013523527131599749848783819988543217424967254479499602698464573208071
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2537.987992 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34449) { a_addr: 'h10628  a_data: 'h4dea118c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h192bd  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2537.987992 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32675) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

10.chip_csr_mem_rw_with_rand_reset.62400615767082928714392137657112071342831549119647139012354993098430361270351
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/10.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2534.405380 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32675) { a_addr: 'h1043c  a_data: 'ha8374cbe  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h37  a_opcode: 'h4  a_user: 'h1b1a7  d_param: 'h0  d_source: 'h37  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2534.405380 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37059) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

11.chip_tl_errors.7183006027107099206756064791210120643509085986358645600164267309509384970037
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/11.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2607.266462 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37059) { a_addr: 'h1037c  a_data: 'h78483d1e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2e  a_opcode: 'h4  a_user: 'h18611  d_param: 'h0  d_source: 'h2e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2607.266462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@271801) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

12.chip_tl_errors.54081124384548201193508832296436441945269065994654823493463035760946967633233
Line 222, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4122.936536 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@271801) { a_addr: 'h106c8  a_data: 'h85c60ce1  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h4  a_user: 'h19235  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4122.936536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32217) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

12.chip_csr_mem_rw_with_rand_reset.100330105573088225379187013060427324730041841134645843139361400948908743965415
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/12.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2332.492750 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32217) { a_addr: 'h10584  a_data: 'hb23e9050  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3c  a_opcode: 'h4  a_user: 'h1aeae  d_param: 'h0  d_source: 'h3c  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2332.492750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31895) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

13.chip_tl_errors.78545512244726519015502533883593770277778046920713279627202591400755196187808
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/13.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2581.989650 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31895) { a_addr: 'h104e8  a_data: 'hfffbd463  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h181cd  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2581.989650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38549) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

14.chip_tl_errors.2539748216081479032398604617962875996388321368378209451743024418682454975521
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2666.172300 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@38549) { a_addr: 'h10414  a_data: 'h42171d6b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h20  a_opcode: 'h4  a_user: 'h1bdcd  d_param: 'h0  d_source: 'h20  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2666.172300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32425) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

14.chip_csr_mem_rw_with_rand_reset.38780505023094949170270522806496392744904704703482959774843756302923734946051
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/14.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2411.624300 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32425) { a_addr: 'h107f4  a_data: 'h897dfee0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h16  a_opcode: 'h4  a_user: 'h1b111  d_param: 'h0  d_source: 'h16  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2411.624300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36475) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

15.chip_tl_errors.102689413736212869993175100852589565180384340588358149762940604949059318364600
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/15.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2440.919816 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36475) { a_addr: 'h10730  a_data: 'h642748cc  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h1a5dc  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2440.919816 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34739) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

16.chip_tl_errors.13601048260217064965331372353824054500888199215318622968367503024907097033606
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2445.521832 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@34739) { a_addr: 'h10610  a_data: 'hed7d370e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb  a_opcode: 'h4  a_user: 'h1ba58  d_param: 'h0  d_source: 'hb  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2445.521832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36039) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

16.chip_csr_mem_rw_with_rand_reset.108809512657296289126883221617085401854377959237104958671675852774440007576351
Line 230, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/16.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2350.021350 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@36039) { a_addr: 'h11d4  a_data: 'h4067110b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h21  a_opcode: 'h1  a_user: 'h2569d  d_param: 'h0  d_source: 'h21  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2350.021350 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39585) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

17.chip_tl_errors.757689451903794068907624204611270808359463729763478059520134093287048119630
Line 230, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2230.056468 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@39585) { a_addr: 'h105d0  a_data: 'haf57bc4e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h1ae23  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2230.056468 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32045) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

17.chip_csr_mem_rw_with_rand_reset.16865363049625446893081469993011601955328578608325091505123929385472867458559
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/17.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2325.434888 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32045) { a_addr: 'h107b0  a_data: 'hadf55d42  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h19549  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2325.434888 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33317) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

18.chip_tl_errors.14753572558685637793208999599438731341384203829621550012556767162732720106151
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2974.910540 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33317) { a_addr: 'h1068c  a_data: 'hbcbd8e05  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3d  a_opcode: 'h4  a_user: 'h1b63c  d_param: 'h0  d_source: 'h3d  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2974.910540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33141) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

18.chip_csr_mem_rw_with_rand_reset.81247545680066760506994699285108708554841503642439946226460694025304656093674
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/18.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2435.710490 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33141) { a_addr: 'h10570  a_data: 'h7c0747b5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h4  a_user: 'h1864b  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2435.710490 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37391) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

19.chip_tl_errors.18229563827052037252001559665213478326269064465346207919737577784730552234248
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_tl_errors/latest/run.log

  UVM_ERROR @ 1793.631100 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@37391) { a_addr: 'h10564  a_data: 'h5c26e1ea  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h1ae1f  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1793.631100 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31931) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

19.chip_csr_mem_rw_with_rand_reset.66898997157895631270979258975925383515273595649783389916548491287370968447264
Line 228, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/19.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 2021.666560 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31931) { a_addr: 'h10430  a_data: 'hbdd7f986  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h4  a_user: 'h1a9fe  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2021.666560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32201) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

20.chip_tl_errors.41817903028800558756053751805065495244110869517915881193890792420445060982898
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/20.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2135.172580 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32201) { a_addr: 'h10650  a_data: 'h4f1e3721  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h10  a_opcode: 'h4  a_user: 'h192d4  d_param: 'h0  d_source: 'h10  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2135.172580 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32789) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

21.chip_tl_errors.59453252763502641203078023105670611648981198929149893139814604878032300110592
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/21.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2625.673162 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32789) { a_addr: 'h105e4  a_data: 'ha5cbd61c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1e  a_opcode: 'h4  a_user: 'h19ead  d_param: 'h0  d_source: 'h1e  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2625.673162 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33973) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

22.chip_tl_errors.2338140176261934622815556228211350655760481822897798126114115103730602670527
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/22.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2477.221576 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33973) { a_addr: 'h107d8  a_data: 'h34d2039  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h7  a_opcode: 'h4  a_user: 'h1b1e9  d_param: 'h0  d_source: 'h7  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2477.221576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@230719) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

23.chip_tl_errors.74555469989011642001238849048590272519632656341019856450970540020564814806740
Line 222, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/23.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3683.948552 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@230719) { a_addr: 'h107dc  a_data: 'hd65492f5  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h17  a_opcode: 'h4  a_user: 'h1bd78  d_param: 'h0  d_source: 'h17  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3683.948552 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33561) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

25.chip_tl_errors.66117400250297153878068532492844758732276032083552953616135290649778103645152
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/25.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2601.593528 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33561) { a_addr: 'h10590  a_data: 'h5539431e  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1b  a_opcode: 'h4  a_user: 'h18685  d_param: 'h0  d_source: 'h1b  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2601.593528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@45691) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

26.chip_tl_errors.74253386758248022418232659308194283244005731897574631922691227333340135156408
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/26.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2194.233172 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@45691) { a_addr: 'h105e4  a_data: 'h738479fa  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3a  a_opcode: 'h4  a_user: 'h19ebe  d_param: 'h0  d_source: 'h3a  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2194.233172 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33921) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

27.chip_tl_errors.30442807675856787206338730159468791728366464842640261013298386958794962902340
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/27.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2769.831970 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@33921) { a_addr: 'h104a8  a_data: 'hbdc20968  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h4  a_user: 'h1a97c  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2769.831970 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31917) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

28.chip_tl_errors.20765057185825627409085469815066355294979350359810122625243851547733195529731
Line 221, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/28.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2086.061038 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@31917) { a_addr: 'h10418  a_data: 'h4b244b6  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h1a5af  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2086.061038 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:521) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35559) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

29.chip_tl_errors.301709423517871919011924582745205198351627823494263936056799298607811511330
Line 230, in log /nightly/runs/scratch/master/chip_earlgrey_asic-sim-vcs/29.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2208.578584 us: (cip_base_scoreboard.sv:521) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@35559) { a_addr: 'h10424  a_data: 'h40deffa2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hd  a_opcode: 'h4  a_user: 'h1818b  d_param: 'h0  d_source: 'hd  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2208.578584 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---