ADC_CTRL Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.940s	6.073ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	6.430s	1.307ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	4.280s	510.344us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	2.530m	50.996ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	6.770s	983.199us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	4.070s	580.943us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	4.280s	510.344us	20	20	100.00
		adc_ctrl_csr_aliasing	6.770s	983.199us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	21.933m	484.775ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	23.098m	477.040ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.607m	495.992ms	48	50	96.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	20.603m	482.547ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.259m	598.902ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	21.729m	606.068ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	21.308m	482.933ms	48	50	96.00
V2	clock_gating	adc_ctrl_clock_gating	21.333m	2.000s	36	50	72.00
V2	poweron_counter	adc_ctrl_poweron_counter	20.230s	5.347ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.294m	41.311ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	7.163m	119.125ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	28.664m	650.739ms	48	50	96.00
V2	alert_test	adc_ctrl_alert_test	3.810s	503.451us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.790s	462.791us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	5.210s	470.864us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	5.210s	470.864us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	6.430s	1.307ms	5	5	100.00
		adc_ctrl_csr_rw	4.280s	510.344us	20	20	100.00
		adc_ctrl_csr_aliasing	6.770s	983.199us	5	5	100.00
		adc_ctrl_same_csr_outstanding	25.790s	4.604ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	6.430s	1.307ms	5	5	100.00
		adc_ctrl_csr_rw	4.280s	510.344us	20	20	100.00
		adc_ctrl_csr_aliasing	6.770s	983.199us	5	5	100.00
		adc_ctrl_same_csr_outstanding	25.790s	4.604ms	20	20	100.00
V2		TOTAL			720	740	97.30
V2S	tl_intg_err	adc_ctrl_sec_cm	22.110s	7.671ms	5	5	100.00
		adc_ctrl_tl_intg_err	23.580s	8.329ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	23.580s	8.329ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	8.265m	10.000s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			898	920	97.61

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.56	99.11	96.45	100.00	100.00	99.01	98.06	90.31

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 13 failures:

Test adc_ctrl_clock_gating has 9 failures.

3.adc_ctrl_clock_gating.107773391998667447936518230755968299054165907866112047624018699165212859792300
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.adc_ctrl_clock_gating.108084288558919079039311916346396981390038587260431473279784022162908666662955
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/12.adc_ctrl_clock_gating/latest/run.log

  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test adc_ctrl_filters_both has 2 failures.

7.adc_ctrl_filters_both.792057222346066844475281031199703142905942643235851759029724052045184963670
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.adc_ctrl_filters_both.24390008320189760785272846588814465966910786484371763451223779515809192502358
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/28.adc_ctrl_filters_both/latest/run.log

  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 9.adc_ctrl_stress_all_with_rand_reset.49806299768494100735118998404375847030675772506848120961726875068369791367389
  Line 232, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/9.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test adc_ctrl_stress_all has 1 failures.

17.adc_ctrl_stress_all.8352138065146776222340590091323942732450253122576129118863884442765885545719
Line 269, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/17.adc_ctrl_stress_all/latest/run.log

  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 5 failures:

Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
- 1.adc_ctrl_stress_all_with_rand_reset.90385876089198616601508844930286349623095312729338524580647462407826151548926
  Line 159, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/1.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5415434133 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 5415434133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test adc_ctrl_clock_gating has 3 failures.

13.adc_ctrl_clock_gating.42193960936896511246934452534845364908931806235323494594682369797226205437848
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/13.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 12028264280 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 12028264280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.adc_ctrl_clock_gating.113478705720730551579042023240398063615697958176314609194501594852102749484141
Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 207860116383 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 207860116383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test adc_ctrl_stress_all has 1 failures.

42.adc_ctrl_stress_all.17644300615643746115930706136429532928230342637152390776277971965705601489325
Line 185, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/42.adc_ctrl_stress_all/latest/run.log

  UVM_ERROR @ 334996735405 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 334996735405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 4 failures:

Test adc_ctrl_clock_gating has 2 failures.

7.adc_ctrl_clock_gating.80340457304832573407937992216346417109345388725148357633125116207015394210559
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/7.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 94340999420 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 94340999420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.adc_ctrl_clock_gating.104230035367503549855605630209935047701169039678527804931960927610878261255497
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/37.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 84197749112 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 84197749112 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_interrupt has 2 failures.

37.adc_ctrl_filters_interrupt.96683856578935073734548082808124079319741540191133343080415651079596686562424
Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/37.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 409903498922 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 409903498922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.adc_ctrl_filters_interrupt.107291816089657104139033303483084329669896756143621738539694476387679842694974
Line 162, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/48.adc_ctrl_filters_interrupt/latest/run.log

  UVM_ERROR @ 244480654176 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 244480654176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---