AES/MASKED Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	62.990us	1	1	100.00
V1	smoke	aes_smoke	11.000s	448.722us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	68.636us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	93.883us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	4.220ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	306.696us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	83.624us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	93.883us	20	20	100.00
		aes_csr_aliasing	6.000s	306.696us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	11.000s	448.722us	50	50	100.00
		aes_config_error	9.000s	361.769us	50	50	100.00
		aes_stress	9.000s	1.078ms	50	50	100.00
V2	key_length	aes_smoke	11.000s	448.722us	50	50	100.00
		aes_config_error	9.000s	361.769us	50	50	100.00
		aes_stress	9.000s	1.078ms	50	50	100.00
V2	back2back	aes_stress	9.000s	1.078ms	50	50	100.00
		aes_b2b	24.000s	1.123ms	50	50	100.00
V2	backpressure	aes_stress	9.000s	1.078ms	50	50	100.00
V2	multi_message	aes_smoke	11.000s	448.722us	50	50	100.00
		aes_config_error	9.000s	361.769us	50	50	100.00
		aes_stress	9.000s	1.078ms	50	50	100.00
		aes_alert_reset	11.000s	577.341us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	62.827us	50	50	100.00
		aes_config_error	9.000s	361.769us	50	50	100.00
		aes_alert_reset	11.000s	577.341us	50	50	100.00
V2	trigger_clear_test	aes_clear	12.000s	412.400us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	14.000s	341.218us	1	1	100.00
V2	reset_recovery	aes_alert_reset	11.000s	577.341us	50	50	100.00
V2	stress	aes_stress	9.000s	1.078ms	50	50	100.00
V2	sideload	aes_stress	9.000s	1.078ms	50	50	100.00
		aes_sideload	12.000s	2.054ms	50	50	100.00
V2	deinitialization	aes_deinit	18.000s	986.751us	50	50	100.00
V2	stress_all	aes_stress_all	46.000s	1.728ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	60.680us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	866.888us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	866.888us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	68.636us	5	5	100.00
		aes_csr_rw	6.000s	93.883us	20	20	100.00
		aes_csr_aliasing	6.000s	306.696us	5	5	100.00
		aes_same_csr_outstanding	6.000s	346.716us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	68.636us	5	5	100.00
		aes_csr_rw	6.000s	93.883us	20	20	100.00
		aes_csr_aliasing	6.000s	306.696us	5	5	100.00
		aes_same_csr_outstanding	6.000s	346.716us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	378.272us	50	50	100.00
V2S	fault_inject	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	337	350	96.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	10.000s	93.815us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	10.000s	93.815us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	10.000s	93.815us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	10.000s	93.815us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	1.066ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	918.261us	5	5	100.00
		aes_tl_intg_err	8.000s	2.254ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	2.254ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	11.000s	577.341us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	10.000s	93.815us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	448.722us	50	50	100.00
		aes_stress	9.000s	1.078ms	50	50	100.00
		aes_alert_reset	11.000s	577.341us	50	50	100.00
		aes_core_fi	25.000s	1.789ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	10.000s	93.815us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	51.943us	50	50	100.00
		aes_stress	9.000s	1.078ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	1.078ms	50	50	100.00
		aes_sideload	12.000s	2.054ms	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	51.943us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	51.943us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	51.943us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	51.943us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	51.943us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	1.078ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	1.078ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	15.000s	1.560ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	337	350	96.29
		aes_ctr_fi	6.000s	122.255us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	15.000s	1.560ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	337	350	96.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	46.000s	10.003ms	337	350	96.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	15.000s	1.560ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_ctr_fi	6.000s	122.255us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	337	350	96.29
		aes_ctr_fi	6.000s	122.255us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	11.000s	577.341us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	337	350	96.29
		aes_ctr_fi	6.000s	122.255us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	337	350	96.29
		aes_ctr_fi	6.000s	122.255us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_ctr_fi	6.000s	122.255us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	15.000s	1.560ms	49	50	98.00
		aes_control_fi	43.000s	10.008ms	279	300	93.00
		aes_cipher_fi	46.000s	10.003ms	337	350	96.29
V2S		TOTAL			948	985	96.24
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	30.000s	2.461ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1555	1602	97.07

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.41	98.62	96.50	99.44	95.70	98.07	97.78	98.96	97.99

Failure Buckets

Job timed out after * minutes has 13 failures:
- Test aes_control_fi has 13 failures.
  - 2.aes_control_fi.15183640599401016808374933589767448867028103445695266593579172551071819916732
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_control_fi.42836893914449064214172889040289122713431807968919328074659618096636143308218
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 2.aes_cipher_fi.34355174118895905957014116384384141276548364583713626241612030597123704761781
    Line 135, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10033249502 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033249502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.aes_cipher_fi.25292896518960405575531262873039271491661020627224553964469915457903528146886
    Line 149, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10021348222 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021348222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 21.aes_control_fi.103695533950125200025898025497600221156148456872909522477776554382262188095313
    Line 133, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006770780 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006770780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 40.aes_control_fi.102824354961551250267081856614466953366366417868235353865413638990943667896551
    Line 132, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/40.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007174295 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007174295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.56956886779402019976927860093802120810389139501204779030791638298746908800070
Line 426, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1112112479 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1112112479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.79751358774078094627137727142278439995459074099889194331642624355836567509578
Line 177, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  45460397 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  45460397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 0.aes_stress_all_with_rand_reset.54056933283699372246097667163413398225351611128767929048143695755298190776052
    Line 526, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2790102850 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 2790102850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.aes_stress_all_with_rand_reset.55202357611146507164555198783499988607255973472472089103272176811100755946032
    Line 719, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 8866053934 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 8866053934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.70053179082782359117936891970908189143390664063136822670453759668265773970327
    Line 136, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 196403956 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 196403956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 28.aes_core_fi.87287488583128032224861948938667609176150763472344799040788551485639834797588
    Line 130, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10040119401 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10040119401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

35.aes_fi.100670085185459087787943668129640593750847793792647155920007414084992229201047
Line 1333, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/35.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 196689984 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 196523317 PS)
  UVM_ERROR @ 196689984 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 196689984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 36.aes_core_fi.53266097591760323442740143748740200641801043518771778551648934867494793312219
    Line 144, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035631964 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035631964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```