AES/UNMASKED Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	115.312us	1	1	100.00
V1	smoke	aes_smoke	7.000s	172.530us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	36.000s	100.010us	5	5	100.00
V1	csr_rw	aes_csr_rw	36.000s	79.596us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	41.000s	593.809us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	37.000s	140.633us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	36.000s	88.268us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	36.000s	79.596us	20	20	100.00
		aes_csr_aliasing	37.000s	140.633us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	7.000s	172.530us	50	50	100.00
		aes_config_error	6.000s	63.190us	50	50	100.00
		aes_stress	7.000s	836.421us	50	50	100.00
V2	key_length	aes_smoke	7.000s	172.530us	50	50	100.00
		aes_config_error	6.000s	63.190us	50	50	100.00
		aes_stress	7.000s	836.421us	50	50	100.00
V2	back2back	aes_stress	7.000s	836.421us	50	50	100.00
		aes_b2b	9.000s	427.229us	50	50	100.00
V2	backpressure	aes_stress	7.000s	836.421us	50	50	100.00
V2	multi_message	aes_smoke	7.000s	172.530us	50	50	100.00
		aes_config_error	6.000s	63.190us	50	50	100.00
		aes_stress	7.000s	836.421us	50	50	100.00
		aes_alert_reset	6.000s	129.385us	49	50	98.00
V2	failure_test	aes_man_cfg_err	6.000s	80.825us	50	50	100.00
		aes_config_error	6.000s	63.190us	50	50	100.00
		aes_alert_reset	6.000s	129.385us	49	50	98.00
V2	trigger_clear_test	aes_clear	8.000s	258.443us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	732.155us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	129.385us	49	50	98.00
V2	stress	aes_stress	7.000s	836.421us	50	50	100.00
V2	sideload	aes_stress	7.000s	836.421us	50	50	100.00
		aes_sideload	7.000s	457.787us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	105.660us	50	50	100.00
V2	stress_all	aes_stress_all	24.000s	1.164ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	52.789us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	37.000s	83.629us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	37.000s	83.629us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	36.000s	100.010us	5	5	100.00
		aes_csr_rw	36.000s	79.596us	20	20	100.00
		aes_csr_aliasing	37.000s	140.633us	5	5	100.00
		aes_same_csr_outstanding	37.000s	312.180us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	36.000s	100.010us	5	5	100.00
		aes_csr_rw	36.000s	79.596us	20	20	100.00
		aes_csr_aliasing	37.000s	140.633us	5	5	100.00
		aes_same_csr_outstanding	37.000s	312.180us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	8.000s	287.710us	50	50	100.00
V2S	fault_inject	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_cipher_fi	36.000s	10.004ms	332	350	94.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	38.000s	247.365us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	38.000s	247.365us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	38.000s	247.365us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	38.000s	247.365us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	38.000s	284.071us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	3.172ms	5	5	100.00
		aes_tl_intg_err	38.000s	149.285us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	38.000s	149.285us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	129.385us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	38.000s	247.365us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	7.000s	172.530us	50	50	100.00
		aes_stress	7.000s	836.421us	50	50	100.00
		aes_alert_reset	6.000s	129.385us	49	50	98.00
		aes_core_fi	2.100m	10.014ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	38.000s	247.365us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	73.606us	50	50	100.00
		aes_stress	7.000s	836.421us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	836.421us	50	50	100.00
		aes_sideload	7.000s	457.787us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	73.606us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	73.606us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	73.606us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	73.606us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	73.606us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	836.421us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	836.421us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	7.000s	102.964us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_cipher_fi	36.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	245.945us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	7.000s	102.964us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_cipher_fi	36.000s	10.004ms	332	350	94.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	36.000s	10.004ms	332	350	94.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	7.000s	102.964us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_ctr_fi	6.000s	245.945us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_cipher_fi	36.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	245.945us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	129.385us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_cipher_fi	36.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	245.945us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_cipher_fi	36.000s	10.004ms	332	350	94.86
		aes_ctr_fi	6.000s	245.945us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_ctr_fi	6.000s	245.945us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	7.000s	102.964us	50	50	100.00
		aes_control_fi	25.000s	10.008ms	280	300	93.33
		aes_cipher_fi	36.000s	10.004ms	332	350	94.86
V2S		TOTAL			944	985	95.84
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	20.000s	391.263us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1550	1602	96.75

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.30	97.66	94.72	98.76	93.60	98.07	91.11	98.85	98.39

Failure Buckets

Job timed out after * minutes has 28 failures:
- Test aes_cipher_fi has 12 failures.
  - 19.aes_cipher_fi.44536448243564064278604711279093446624189703511458818727054416395089903089219
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 87.aes_cipher_fi.105430737414706956561603351258916921274851123201310574989744053599224945020063
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/87.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
- Test aes_control_fi has 16 failures.
  - 56.aes_control_fi.47498366349894305312030455386618030072925507092890576428698365224069511131890
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 82.aes_control_fi.59080414190316968716962300459666893852509177025990436360537286305589433513283
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/82.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 14 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.42710945366275960272000729630902056972316763629040119761332053587419744581113
Line 1340, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2493827311 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2493827311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.35400006434132192627281446516964432148009979379882627164970220462868595247629
Line 1273, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 391263136 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 391263136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 59.aes_cipher_fi.85604551109433087356864703610276593479970484426832872125778961279815227060633
    Line 147, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006809298 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006809298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 163.aes_cipher_fi.44972723604209232703196542569807876573763062436505587687331529598601668145723
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/163.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004042353 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004042353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 47.aes_control_fi.19502003249908970263458003491627794860641778643416277564933180805321212222850
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/47.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10032266541 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032266541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 55.aes_control_fi.96887392094073844008196291009691652728380241500236394975631173927064353212104
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005823186 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005823186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 62.aes_core_fi.85810446942043846276688357479561159322767488323990421601315859970660844124521
    Line 137, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008945865 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008945865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 65.aes_core_fi.92838474949820030068734706617125395531767089920449504086631666109501671572512
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10039475900 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039475900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 0.aes_core_fi.106281645530973069824381165029072475654946538418047552276985543914570150193912
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013519922 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xa0e68184, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10013519922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:908) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.81958445044156548899099815468651576742131424549488922489802763162699676486913
    Line 144, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 883903586 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 883903586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.58587851013845122051319831804545940759845000380144971210602311532488403380167
    Line 951, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1516757943 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1516757943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.104607957994474917400090829153891962098996650539601231118057386378862075032346
    Line 448, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1681693278 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1681693278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

37.aes_alert_reset.55912949546431530734294057981116651946157911635550164378564896564219559666998
Line 752, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/37.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 5879777 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 5858944 PS)
  UVM_ERROR @   5879777 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   5879777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_cipher_fi has 1 failures.

267.aes_cipher_fi.28327420521328725423399063711421016144553367390308008023508402468599742082638
Line 136, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/267.aes_cipher_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 5697177 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 5687177 PS)
  UVM_ERROR @   5697177 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   5697177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---