CSRNG Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	8.000s	169.055us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	59.249us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	45.234us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	19.000s	1.128ms	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	7.000s	154.129us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	8.000s	234.802us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	45.234us	20	20	100.00
		csrng_csr_aliasing	7.000s	154.129us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	22.000s	1.106ms	200	200	100.00
V2	alerts	csrng_alert	1.283m	7.200ms	500	500	100.00
V2	err	csrng_err	8.000s	55.233us	500	500	100.00
V2	cmds	csrng_cmds	11.833m	60.036ms	50	50	100.00
V2	life cycle	csrng_cmds	11.833m	60.036ms	50	50	100.00
V2	stress_all	csrng_stress_all	31.367m	176.122ms	50	50	100.00
V2	intr_test	csrng_intr_test	6.000s	38.878us	50	50	100.00
V2	alert_test	csrng_alert_test	9.000s	103.791us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	10.000s	229.411us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	10.000s	229.411us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	59.249us	5	5	100.00
		csrng_csr_rw	6.000s	45.234us	20	20	100.00
		csrng_csr_aliasing	7.000s	154.129us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	39.957us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	59.249us	5	5	100.00
		csrng_csr_rw	6.000s	45.234us	20	20	100.00
		csrng_csr_aliasing	7.000s	154.129us	5	5	100.00
		csrng_same_csr_outstanding	7.000s	39.957us	20	20	100.00
V2		TOTAL			1440	1440	100.00
V2S	tl_intg_err	csrng_sec_cm	7.000s	349.816us	5	5	100.00
		csrng_tl_intg_err	14.000s	501.646us	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	8.000s	35.143us	50	50	100.00
		csrng_csr_rw	6.000s	45.234us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.283m	7.200ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	31.367m	176.122ms	50	50	100.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.283m	7.200ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	31.367m	176.122ms	50	50	100.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.283m	7.200ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	14.000s	501.646us	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
		csrng_sec_cm	7.000s	349.816us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	22.000s	1.106ms	200	200	100.00
		csrng_err	8.000s	55.233us	500	500	100.00
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.800m	4.416ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1620	1630	99.39

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.75	98.61	96.63	99.94	97.36	92.08	100.00	97.36	90.72

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:908) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 9 failures:
  • Test csrng_stress_all_with_rand_reset has 9 failures.

    • 0.csrng_stress_all_with_rand_reset.56152939658560112437117769089539668330117637924062192811312250044813163835291
      Line 111, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2367329378 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2367329378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.csrng_stress_all_with_rand_reset.82910659324586100090840580216813157062366942061470752473944666573672255979272
      Line 109, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1748823101 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1748823101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 7 more failures.

• UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started has 1 failures:
  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 6.csrng_stress_all_with_rand_reset.27393998011783836134746508887351734846397825886723158611468014513636262938756
      Line 104, in log /nightly/runs/scratch/master/csrng-sim-xcelium/6.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  15343117 ps: uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer [SEQ_NOT_DONE] Sequence uvm_test_top.env.m_edn_agent[1].m_cmd_push_agent.sequencer.m_edn_push_seq[1] already started
        UVM_INFO @  15343117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---