EDN Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	3.880s	19.017us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	2.080s	23.563us	5	5	100.00
V1	csr_rw	edn_csr_rw	2.530s	28.734us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.710s	352.692us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.320s	35.835us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	3.080s	32.441us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	2.530s	28.734us	20	20	100.00
		edn_csr_aliasing	2.320s	35.835us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	7.860s	1.216ms	300	300	100.00
V2	csrng_commands	edn_genbits	7.860s	1.216ms	300	300	100.00
V2	genbits	edn_genbits	7.860s	1.216ms	300	300	100.00
V2	interrupts	edn_intr	3.900s	22.069us	50	50	100.00
V2	alerts	edn_alert	3.950s	87.727us	200	200	100.00
V2	errs	edn_err	4.120s	30.343us	100	100	100.00
V2	disable	edn_disable	3.750s	44.686us	50	50	100.00
		edn_disable_auto_req_mode	4.030s	56.759us	50	50	100.00
V2	stress_all	edn_stress_all	9.120s	433.347us	50	50	100.00
V2	intr_test	edn_intr_test	2.470s	44.683us	50	50	100.00
V2	alert_test	edn_alert_test	3.800s	14.426us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	6.050s	145.391us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	6.050s	145.391us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	2.080s	23.563us	5	5	100.00
		edn_csr_rw	2.530s	28.734us	20	20	100.00
		edn_csr_aliasing	2.320s	35.835us	5	5	100.00
		edn_same_csr_outstanding	2.590s	20.625us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	2.080s	23.563us	5	5	100.00
		edn_csr_rw	2.530s	28.734us	20	20	100.00
		edn_csr_aliasing	2.320s	35.835us	5	5	100.00
		edn_same_csr_outstanding	2.590s	20.625us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	9.920s	552.162us	5	5	100.00
		edn_tl_intg_err	5.830s	947.918us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	3.870s	16.384us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	3.950s	87.727us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.920s	552.162us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.920s	552.162us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.920s	552.162us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.920s	552.162us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	3.950s	87.727us	200	200	100.00
		edn_sec_cm	9.920s	552.162us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	3.950s	87.727us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	5.830s	947.918us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.768h	10.000s	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1110	1130	98.23

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.87	98.32	94.23	97.02	91.86	96.36	99.78	93.51

Failure Buckets

• Job timed out after * minutes has 19 failures:
  • Test edn_stress_all_with_rand_reset has 19 failures.

    • 2.edn_stress_all_with_rand_reset.27381005629244984405997813562921226111021465080332020611477993166148571688599
      Log /nightly/runs/scratch/master/edn-sim-vcs/2.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • 3.edn_stress_all_with_rand_reset.24102001299888098282814157224997928950646930364664899257949484224915077444411
      Log /nightly/runs/scratch/master/edn-sim-vcs/3.edn_stress_all_with_rand_reset/latest/run.log

        Job timed out after 180 minutes
      

    • ... and 17 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test edn_stress_all_with_rand_reset has 1 failures.

    • 21.edn_stress_all_with_rand_reset.48604503493646208145945948064545673863775039366034674191252520733285928586323
      Line 409, in log /nightly/runs/scratch/master/edn-sim-vcs/21.edn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---