ENTROPY_SRC Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 35.198us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 34.000s 32.169us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 33.000s 27.745us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 37.000s 334.708us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 36.000s 602.722us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 30.000s 315.483us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 33.000s 27.745us 20 20 100.00
entropy_src_csr_aliasing 36.000s 602.722us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 35.198us 50 50 100.00
entropy_src_rng 4.700m 10.058ms 17 300 5.67
entropy_src_fw_ov 8.600m 19.094ms 175 300 58.33
V2 firmware_mode entropy_src_fw_ov 8.600m 19.094ms 175 300 58.33
V2 rng_mode entropy_src_rng 4.700m 10.058ms 17 300 5.67
V2 rng_max_rate entropy_src_rng_max_rate 5.333m 7.064ms 7 400 1.75
V2 health_checks entropy_src_rng 4.700m 10.058ms 17 300 5.67
V2 conditioning entropy_src_rng 4.700m 10.058ms 17 300 5.67
V2 interrupts entropy_src_rng 4.700m 10.058ms 17 300 5.67
entropy_src_intr 38.000s 1.227ms 50 50 100.00
V2 alerts entropy_src_rng 4.700m 10.058ms 17 300 5.67
entropy_src_functional_alerts 7.000s 74.705us 50 50 100.00
V2 stress_all entropy_src_stress_all 7.767m 19.206ms 45 50 90.00
V2 functional_errors entropy_src_functional_errors 7.717m 10.013ms 960 1000 96.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 33.000s 352.221us 50 50 100.00
V2 intr_test entropy_src_intr_test 36.000s 22.188us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 56.179us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 38.000s 558.175us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 38.000s 558.175us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 34.000s 32.169us 5 5 100.00
entropy_src_csr_rw 33.000s 27.745us 20 20 100.00
entropy_src_csr_aliasing 36.000s 602.722us 5 5 100.00
entropy_src_same_csr_outstanding 33.000s 30.613us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 34.000s 32.169us 5 5 100.00
entropy_src_csr_rw 33.000s 27.745us 20 20 100.00
entropy_src_csr_aliasing 36.000s 602.722us 5 5 100.00
entropy_src_same_csr_outstanding 33.000s 30.613us 20 20 100.00
V2 TOTAL 1494 2340 63.85
V2S tl_intg_err entropy_src_sec_cm 6.000s 90.119us 5 5 100.00
entropy_src_tl_intg_err 37.000s 88.301us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.700m 10.058ms 17 300 5.67
entropy_src_cfg_regwen 6.000s 59.853us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.700m 10.058ms 17 300 5.67
V2S sec_cm_config_redun entropy_src_rng 4.700m 10.058ms 17 300 5.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.700m 10.058ms 17 300 5.67
entropy_src_fw_ov 8.600m 19.094ms 175 300 58.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 7.717m 10.013ms 960 1000 96.00
entropy_src_sec_cm 6.000s 90.119us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 7.717m 10.013ms 960 1000 96.00
entropy_src_sec_cm 6.000s 90.119us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.700m 10.058ms 17 300 5.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 7.717m 10.013ms 960 1000 96.00
entropy_src_sec_cm 6.000s 90.119us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 7.717m 10.013ms 960 1000 96.00
entropy_src_sec_cm 6.000s 90.119us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 7.717m 10.013ms 960 1000 96.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 7.000s 74.705us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 37.000s 88.301us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.267m 12.083ms 8 50 16.00
V3 TOTAL 8 50 16.00
TOTAL 1682 2570 65.45

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
95.95 98.13 95.28 98.33 95.41 96.32 96.88 91.01 85.76

Failure Buckets