HMAC Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	14.850s	11.150ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.350s	132.345us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.500s	30.226us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.750s	1.286ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	8.570s	2.476ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.161m	322.552ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.500s	30.226us	20	20	100.00
		hmac_csr_aliasing	8.570s	2.476ms	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	1.395m	36.155ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.720m	6.879ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	3.935m	19.109ms	30	30	100.00
		hmac_test_sha384_vectors	8.863m	57.168ms	75	75	100.00
		hmac_test_sha512_vectors	8.928m	15.048ms	75	75	100.00
		hmac_test_hmac256_vectors	15.250s	352.661us	50	50	100.00
		hmac_test_hmac384_vectors	17.780s	379.380us	60	60	100.00
		hmac_test_hmac512_vectors	20.090s	389.562us	75	75	100.00
V2	burst_wr	hmac_burst_wr	48.060s	2.889ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	18.626m	7.312ms	10	10	100.00
V2	error	hmac_error	1.377m	26.040ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.535m	2.278ms	10	10	100.00
V2	save_and_restore	hmac_smoke	14.850s	11.150ms	10	10	100.00
		hmac_long_msg	1.395m	36.155ms	10	10	100.00
		hmac_back_pressure	1.720m	6.879ms	25	25	100.00
		hmac_datapath_stress	18.626m	7.312ms	10	10	100.00
		hmac_burst_wr	48.060s	2.889ms	50	50	100.00
		hmac_stress_all	41.418m	85.002ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	14.850s	11.150ms	10	10	100.00
		hmac_long_msg	1.395m	36.155ms	10	10	100.00
		hmac_back_pressure	1.720m	6.879ms	25	25	100.00
		hmac_datapath_stress	18.626m	7.312ms	10	10	100.00
		hmac_wipe_secret	1.535m	2.278ms	10	10	100.00
		hmac_test_sha256_vectors	3.935m	19.109ms	30	30	100.00
		hmac_test_sha384_vectors	8.863m	57.168ms	75	75	100.00
		hmac_test_sha512_vectors	8.928m	15.048ms	75	75	100.00
		hmac_test_hmac256_vectors	15.250s	352.661us	50	50	100.00
		hmac_test_hmac384_vectors	17.780s	379.380us	60	60	100.00
		hmac_test_hmac512_vectors	20.090s	389.562us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	14.850s	11.150ms	10	10	100.00
		hmac_long_msg	1.395m	36.155ms	10	10	100.00
		hmac_back_pressure	1.720m	6.879ms	25	25	100.00
		hmac_datapath_stress	18.626m	7.312ms	10	10	100.00
		hmac_burst_wr	48.060s	2.889ms	50	50	100.00
		hmac_error	1.377m	26.040ms	10	10	100.00
		hmac_wipe_secret	1.535m	2.278ms	10	10	100.00
		hmac_test_sha256_vectors	3.935m	19.109ms	30	30	100.00
		hmac_test_sha384_vectors	8.863m	57.168ms	75	75	100.00
		hmac_test_sha512_vectors	8.928m	15.048ms	75	75	100.00
		hmac_test_hmac256_vectors	15.250s	352.661us	50	50	100.00
		hmac_test_hmac384_vectors	17.780s	379.380us	60	60	100.00
		hmac_test_hmac512_vectors	20.090s	389.562us	75	75	100.00
		hmac_stress_all	41.418m	85.002ms	50	50	100.00
V2	stress_all	hmac_stress_all	41.418m	85.002ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.140s	43.316us	50	50	100.00
V2	intr_test	hmac_intr_test	2.190s	51.501us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.330s	219.295us	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.330s	219.295us	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.350s	132.345us	5	5	100.00
		hmac_csr_rw	2.500s	30.226us	20	20	100.00
		hmac_csr_aliasing	8.570s	2.476ms	5	5	100.00
		hmac_same_csr_outstanding	4.000s	151.424us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.350s	132.345us	5	5	100.00
		hmac_csr_rw	2.500s	30.226us	20	20	100.00
		hmac_csr_aliasing	8.570s	2.476ms	5	5	100.00
		hmac_same_csr_outstanding	4.000s	151.424us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	2.610s	1.082ms	5	5	100.00
		hmac_tl_intg_err	5.910s	289.493us	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	5.910s	289.493us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	14.850s	11.150ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	8.270s	479.652us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	6.130m	25.668ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.950s	13.088us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.06	100.00	97.14	100.00	100.00	100.00	100.00	47.30