I2C Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.426m	20.968ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	33.070s	5.457ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.620s	22.382us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.570s	79.755us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	6.260s	2.102ms	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.030s	29.864us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.870s	25.635us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.570s	79.755us	20	20	100.00
		i2c_csr_aliasing	3.030s	29.864us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	13.140s	295.396us	50	50	100.00
V2	host_stress_all	i2c_host_stress_all	39.737m	34.356ms	15	50	30.00
V2	host_maxperf	i2c_host_perf	47.897m	48.921ms	50	50	100.00
V2	host_override	i2c_host_override	2.230s	40.017us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	4.313m	5.058ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.244m	11.875ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.890s	151.113us	50	50	100.00
		i2c_host_fifo_fmt_empty	26.830s	662.944us	50	50	100.00
		i2c_host_fifo_reset_rx	13.820s	243.795us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.748m	3.032ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	35.030s	888.320us	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	7.680s	699.713us	19	50	38.00
V2	target_glitch	i2c_target_glitch	10.710s	10.909ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	33.013m	62.461ms	50	50	100.00
V2	target_maxperf	i2c_target_perf	8.940s	911.643us	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.197m	8.785ms	50	50	100.00
		i2c_target_intr_smoke	10.270s	5.345ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.340s	281.485us	50	50	100.00
		i2c_target_fifo_reset_tx	3.450s	266.814us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	16.790m	56.891ms	50	50	100.00
		i2c_target_stress_rd	1.197m	8.785ms	50	50	100.00
		i2c_target_intr_stress_wr	6.297m	24.951ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	10.310s	6.272ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	1.976m	4.510ms	45	50	90.00
V2	bad_address	i2c_target_bad_addr	9.130s	5.604ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	44.690s	10.316ms	23	50	46.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.660s	733.403us	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.160s	321.886us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	47.897m	48.921ms	50	50	100.00
		i2c_host_perf_precise	5.894m	5.801ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	35.030s	888.320us	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	18.850s	1.221ms	46	50	92.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.500s	626.103us	50	50	100.00
		i2c_target_nack_acqfull_addr	4.780s	1.097ms	50	50	100.00
		i2c_target_nack_txstretch	3.540s	241.856us	39	50	78.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	26.460s	648.689us	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.930s	1.188ms	50	50	100.00
V2	alert_test	i2c_alert_test	2.100s	19.569us	50	50	100.00
V2	intr_test	i2c_intr_test	2.480s	21.091us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	4.150s	171.777us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	4.150s	171.777us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.620s	22.382us	5	5	100.00
		i2c_csr_rw	2.570s	79.755us	20	20	100.00
		i2c_csr_aliasing	3.030s	29.864us	5	5	100.00
		i2c_same_csr_outstanding	2.660s	56.327us	20	20	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.620s	22.382us	5	5	100.00
		i2c_csr_rw	2.570s	79.755us	20	20	100.00
		i2c_csr_aliasing	3.030s	29.864us	5	5	100.00
		i2c_same_csr_outstanding	2.660s	56.327us	20	20	100.00
V2		TOTAL			1679	1792	93.69
V2S	tl_intg_err	i2c_tl_intg_err	3.630s	279.747us	20	20	100.00
		i2c_sec_cm	2.590s	69.335us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.630s	279.747us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	26.330s	2.591ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	3.870s	1.118ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	55.860s	10.566ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1859	2042	91.04

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.20	97.35	89.82	74.17	72.62	94.34	98.52	90.59

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 45 failures:

Test i2c_host_stress_all has 27 failures.

1.i2c_host_stress_all.22790676316283415139547168397867687127013142272007923176697311846215204570026
Line 120, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 43116656370 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1781874

4.i2c_host_stress_all.45986344800787779787893138323464706001437575521899954384451165820967919846791
Line 248, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 21550701229 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @9693068

... and 25 more failures.

Test i2c_host_mode_toggle has 18 failures.

4.i2c_host_mode_toggle.61804047807815596542075566692008092451849485483841860677448052943943773275793
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 226535476 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @64401

8.i2c_host_mode_toggle.63164633957942573244657211807252811891244037520862792614926469599750052757547
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 481232349 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @37909

... and 16 more failures.

UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 27 failures:
- Test i2c_target_hrst has 27 failures.
  - 0.i2c_target_hrst.59816113346411022502686511686562407546950307157451615464758818890170375404901
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10020361886 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10020361886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_hrst.1266301779982608051431258385483905629680998858229360926111113830736818274669
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10283447824 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10283447824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 25 more failures.
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 26 failures:
- Test i2c_target_unexp_stop has 26 failures.
  - 2.i2c_target_unexp_stop.39541930638421878129152512092625304393086433796013845745829316618267309950133
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  66587250 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 252 [0xfc])
  UVM_INFO @  66587250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.22162447498752317546543802278909021894816795571862709304909231233812620328521
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 1290491101 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 233 [0xe9])
  UVM_INFO @ 1290491101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 24 more failures.
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 20 failures:
- Test i2c_target_unexp_stop has 20 failures.
  - 0.i2c_target_unexp_stop.104489784917613022419256843262350795569730379631839901872045375389245358046116
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 148641943 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 148641943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.84847501283629352276600703684753680259473931025405155013897788653345084872356
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  10959820 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  10959820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.

UVM_ERROR (cip_base_vseq.sv:907) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.32767562147798890764216293457033122872495317561944884081646505580154843406756
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 278185625 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 278185625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.55876718588951629127885602416068428054806975133700542138533171761055477708653
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 154749025 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 154749025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 7 failures.

2.i2c_target_stress_all_with_rand_reset.20054008861077210812046282501979109120425493006011868237488721755601468900265
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 437278360 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 437278360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.i2c_target_stress_all_with_rand_reset.5136215284533225297807960334138743672139155439477238021452472372213325043164
Line 123, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3436616709 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3436616709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 11 failures:
- Test i2c_target_nack_txstretch has 11 failures.
  - 1.i2c_target_nack_txstretch.95128160888870366270352208266629996942297074121267614872786169396267029129261
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 182368046 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 182368046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_nack_txstretch.37663703485751787976232521521898585703371922830385337290068262591743286368404
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 188085275 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 188085275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 10 failures:

Test i2c_host_mode_toggle has 10 failures.

1.i2c_host_mode_toggle.92586293268216542826286856925814831408621901583588844698379186573067509656647
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  93908273 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

7.i2c_host_mode_toggle.53721729833030132962348911253941897832793791772843921197797229445437429618428
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 199587648 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 8 more failures.

Job timed out after * minutes has 5 failures:
- Test i2c_host_stress_all has 4 failures.
  - 0.i2c_host_stress_all.103486058935733690017373634206526508254744404112437851725020342321458499108733
    Log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - 3.i2c_host_stress_all.9744061180714641004217734342209601691933977800716809235722388085875125002002
    Log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
  - ... and 2 more failures.
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 1.i2c_target_stress_all_with_rand_reset.35899365267205895838641616302166656157902346492605336044649270726382427745877
    Log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 20 minutes
```
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 5 failures:
- Test i2c_target_stretch has 5 failures.
  - 4.i2c_target_stretch.9055758626664516300541381084431887293846929637574742204791681441723202638929
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10004660688 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10004660688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 7.i2c_target_stretch.53794389780613474235080388628258707061278726777207194460688533697707638119865
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10045233206 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10045233206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 4 failures.
  - 14.i2c_target_tx_stretch_ctrl.12231161800320303751659558043832674437751547944450086848544841878397716186299
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/14.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 27.i2c_target_tx_stretch_ctrl.40541292131611921786303920778599244496673469598961699917164803604607148023135
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/27.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 4 failures:

Test i2c_target_unexp_stop has 4 failures.

20.i2c_target_unexp_stop.47307814325915284108128642608266568570976570870748780140050740152282274561128
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 186756214 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 186756214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.i2c_target_unexp_stop.20993153296622396013324676567810245176196458171916138601502590559541554106980
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/29.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 138735321 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 138735321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:

Test i2c_host_stress_all has 3 failures.

20.i2c_host_stress_all.114550282189383668069188383660637612169191517040182600529764231647056092201109
Line 185, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 13527064622 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @16106412

42.i2c_host_stress_all.30794982709049989340717749935059456926722157323253649256130330113723153001925
Line 423, in log /nightly/runs/scratch/master/i2c-sim-vcs/42.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 38474596838 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @2452422

... and 1 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 3 failures:
- Test i2c_host_mode_toggle has 3 failures.
  - 21.i2c_host_mode_toggle.25646916012367333730281878883052097788032885230008265172103819947260148621355
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/21.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  55101625 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x68ce5b94, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  55101625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 36.i2c_host_mode_toggle.97898038678033979488367242479566079511434416351508438478683521395671335948133
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/36.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  45317626 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xaa1f1514, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  45317626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:811) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 0.i2c_target_stress_all_with_rand_reset.84758728294050583648537110661962918594869537981509406140315890096264297228788
    Line 85, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 812973924 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 812973924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.i2c_target_stress_all_with_rand_reset.18120208369348322369151548650016797832630236068088599636594716010402843334245
    Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1474009378 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1474009378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=1480) has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 19.i2c_host_stress_all.110169580253634681503040467256574399763451385988907486188365860581657041448677
    Line 88, in log /nightly/runs/scratch/master/i2c-sim-vcs/19.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 44329607829 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.fmtfull (addr=0x34eb1a14, Comparison=CompareOpEq, exp_data=0x0, call_count=1480)
  UVM_INFO @ 44329607829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```