KEYMGR Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	19.140s	943.016us	49	50	98.00
V1	random	keymgr_random	48.500s	5.069ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.680s	17.002us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	3.050s	43.113us	13	20	65.00
V1	csr_bit_bash	keymgr_csr_bit_bash	20.640s	3.440ms	2	5	40.00
V1	csr_aliasing	keymgr_csr_aliasing	15.410s	373.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.390s	36.430us	14	20	70.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	3.050s	43.113us	13	20	65.00
		keymgr_csr_aliasing	15.410s	373.161us	5	5	100.00
V1		TOTAL			138	155	89.03
V2	cfgen_during_op	keymgr_cfg_regwen	36.850s	3.894ms	49	50	98.00
V2	sideload	keymgr_sideload	39.720s	7.102ms	50	50	100.00
		keymgr_sideload_kmac	37.530s	1.391ms	50	50	100.00
		keymgr_sideload_aes	43.410s	9.044ms	50	50	100.00
		keymgr_sideload_otbn	1.157m	3.808ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	33.280s	6.140ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	15.570s	393.554us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	12.690s	528.734us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	35.240s	6.467ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	27.710s	3.163ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	17.630s	1.075ms	50	50	100.00
V2	stress_all	keymgr_stress_all	4.024m	56.460ms	48	50	96.00
V2	intr_test	keymgr_intr_test	2.440s	11.774us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.510s	11.546us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.310s	1.292ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.310s	1.292ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.680s	17.002us	5	5	100.00
		keymgr_csr_rw	3.050s	43.113us	13	20	65.00
		keymgr_csr_aliasing	15.410s	373.161us	5	5	100.00
		keymgr_same_csr_outstanding	3.220s	338.341us	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.680s	17.002us	5	5	100.00
		keymgr_csr_rw	3.050s	43.113us	13	20	65.00
		keymgr_csr_aliasing	15.410s	373.161us	5	5	100.00
		keymgr_same_csr_outstanding	3.220s	338.341us	14	20	70.00
V2		TOTAL			728	740	98.38
V2S	sec_cm_additional_check	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
		keymgr_tl_intg_err	8.780s	263.489us	15	20	75.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.400s	200.741us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.400s	200.741us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.400s	200.741us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.400s	200.741us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	9.690s	506.705us	13	20	65.00
V2S	prim_count_check	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	8.780s	263.489us	15	20	75.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.400s	200.741us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	36.850s	3.894ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	48.500s	5.069ms	50	50	100.00
		keymgr_csr_rw	3.050s	43.113us	13	20	65.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	48.500s	5.069ms	50	50	100.00
		keymgr_csr_rw	3.050s	43.113us	13	20	65.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	48.500s	5.069ms	50	50	100.00
		keymgr_csr_rw	3.050s	43.113us	13	20	65.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	15.570s	393.554us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	27.710s	3.163ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	27.710s	3.163ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	48.500s	5.069ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	18.810s	1.174ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	32.140s	12.465ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	15.570s	393.554us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	32.140s	12.465ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	32.140s	12.465ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	32.140s	12.465ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	13.660s	996.363us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	32.140s	12.465ms	50	50	100.00
V2S		TOTAL			153	165	92.73
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.840s	739.152us	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1049	1110	94.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.10	98.15	98.48	100.00	99.02	98.63	91.18

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 34 failures:

Test keymgr_csr_bit_bash has 3 failures.

0.keymgr_csr_bit_bash.91575639275950122988809707006750583275586967352515816430934342734360393851508
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @ 3278976082 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @ 3278976082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.keymgr_csr_bit_bash.73482578793052356236717464601796281224724926167473102911734920522081001857314
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @ 820443866 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @ 820443866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test keymgr_tl_intg_err has 5 failures.

1.keymgr_tl_intg_err.79025743185179790964553876809766576751893565764773988365145523342812852782423
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @  88568882 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @  88568882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_tl_intg_err.6934455550775336186346488475609974488507319764387308640583018023989837270034
Line 107, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @ 187989372 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @ 187989372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_mem_rw_with_rand_reset has 6 failures.

1.keymgr_csr_mem_rw_with_rand_reset.50758719378451686450344666020750704368751661642868635462136621422294308063914
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  27657188 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  27657188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.keymgr_csr_mem_rw_with_rand_reset.24858268629684886102954011986728937631613984263693557961571918340211798831143
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @   9934633 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @   9934633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_same_csr_outstanding has 6 failures.

2.keymgr_same_csr_outstanding.67268511212934214693706386692642868250178870882463483403076108431932220126550
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @  97870550 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @  97870550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.keymgr_same_csr_outstanding.10994973997657473861798659651487140991604239268684994870083183971064600920771
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
  UVM_ERROR @  38333852 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
  UVM_INFO @  38333852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_rw has 7 failures.

3.keymgr_csr_rw.103959213487423386173421819764239339655890790132113384437415097061289882281517
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  22743593 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  22743593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.keymgr_csr_rw.87392383764064510774484010701208614209314917586008653554495314820817427404559
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[13] & 'hffffffff)))'
  UVM_ERROR @   6967236 ps: (keymgr_csr_assert_fpv.sv:431) [ASSERT FAILED] attest_sw_binding_0_rd_A
  UVM_INFO @   6967236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

... and 1 more tests.

UVM_ERROR (cip_base_vseq.sv:907) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test keymgr_stress_all_with_rand_reset has 20 failures.
  - 6.keymgr_stress_all_with_rand_reset.63067787049609796042329957794812494864729719318674458970806789502687805109986
    Line 403, in log /nightly/runs/scratch/master/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 239295870 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 239295870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.keymgr_stress_all_with_rand_reset.18828755591494405385925271238201377282443841280702027240771981030638632365607
    Line 97, in log /nightly/runs/scratch/master/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 425481370 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 425481370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 18 more failures.

UVM_ERROR (cip_base_scoreboard.sv:333) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_sw_invalid_input has 1 failures.

20.keymgr_sw_invalid_input.54487153459222608884652393020857730616795000055259713109791114949375414716574
Line 291, in log /nightly/runs/scratch/master/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @  24342645 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  24342645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_lc_disable has 1 failures.

39.keymgr_lc_disable.55036143129031664997528006371492679859437135719677500689855401791064755520895
Line 141, in log /nightly/runs/scratch/master/keymgr-sim-vcs/39.keymgr_lc_disable/latest/run.log

  UVM_ERROR @   3953535 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   3953535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_smoke has 1 failures.

41.keymgr_smoke.102572017936258169929378917083794795336602746361479496086195266633667194722015
Line 94, in log /nightly/runs/scratch/master/keymgr-sim-vcs/41.keymgr_smoke/latest/run.log

  UVM_ERROR @  14529479 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  14529479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_stress_all has 1 failures.

47.keymgr_stress_all.65558130603815468170761902912163397184771013174220595699355897284962913486676
Line 104, in log /nightly/runs/scratch/master/keymgr-sim-vcs/47.keymgr_stress_all/latest/run.log

  UVM_ERROR @  17615851 ps: (cip_base_scoreboard.sv:333) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  17615851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Sealing Kmac has 1 failures:

Test keymgr_stress_all has 1 failures.

8.keymgr_stress_all.95130684596333462413720651238872702319995970288818008954763870860529474854078
Line 2512, in log /nightly/runs/scratch/master/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1301483265 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (2013049548209631389674595904986990650118872757160406863025124602096120867770956388841408917042497030853518880893869567121762385912133464322318606948360555 [0x266f94cb3ce2e41392152353c798cb56d6f360924c5bcbe0bb3347d9aaba0951d232e9ea089358894eb4b06bf9a0b14dbc444602445236d040e6e68fbe07e16b] vs 2013049548209631389674595904986990650118872757160406863025124602096120867770956388841408917042497030853518880893869567121762385912133464322318606948360555 [0x266f94cb3ce2e41392152353c798cb56d6f360924c5bcbe0bb3347d9aaba0951d232e9ea089358894eb4b06bf9a0b14dbc444602445236d040e6e68fbe07e16b]) KMAC key at state StDisabled for Sealing Kmac
  UVM_INFO @ 1301483265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerKey for Sealing Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

44.keymgr_lc_disable.26909333354283587372809801101228238537503910916195302498139402790814138826772
Line 532, in log /nightly/runs/scratch/master/keymgr-sim-vcs/44.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  94241238 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (9706861511463556513704511033177194159486634183776052085797813162653059422098057766901698045597597986863554168287028133506308112305651769321190226651287234 [0xb95626964d3233e80a020961e87d820aec5ff56e8ac51ad3d264f30d3ff538acc2a6cb237b3a11452989bcacdaa22b0d4fc37dbef393757df96df7517a248ec2] vs 9706861511463556513704511033177194159486634183776052085797813162653059422098057766901698045597597986863554168287028133506308112305651769321190226651287234 [0xb95626964d3233e80a020961e87d820aec5ff56e8ac51ad3d264f30d3ff538acc2a6cb237b3a11452989bcacdaa22b0d4fc37dbef393757df96df7517a248ec2]) KMAC key at state StOwnerKey for Sealing Kmac
  UVM_INFO @  94241238 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:263) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_cfg_regwen has 1 failures.
  - 48.keymgr_cfg_regwen.77288091511354338386375149859273385683496463576098797819091339058783160188419
    Line 380, in log /nightly/runs/scratch/master/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @  27434239 ps: (cip_base_scoreboard.sv:263) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  27434239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```