KMAC/MASKED Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.548m	5.085ms	48	50	96.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.800s	69.860us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.670s	93.953us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.010s	3.352ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.020s	795.625us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.800s	76.613us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.670s	93.953us	20	20	100.00
		kmac_csr_aliasing	10.020s	795.625us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.230s	11.029us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.980s	73.532us	5	5	100.00
V1		TOTAL			113	115	98.26
V2	long_msg_and_output	kmac_long_msg_and_output	59.788m	424.488ms	50	50	100.00
V2	burst_write	kmac_burst_write	23.902m	116.964ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.876m	376.981ms	5	5	100.00
		kmac_test_vectors_sha3_256	31.029m	816.031ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.816m	280.972ms	5	5	100.00
		kmac_test_vectors_sha3_512	17.920m	10.110ms	5	5	100.00
		kmac_test_vectors_shake_128	41.726m	70.824ms	5	5	100.00
		kmac_test_vectors_shake_256	25.076m	17.889ms	5	5	100.00
		kmac_test_vectors_kmac	4.620s	80.040us	5	5	100.00
		kmac_test_vectors_kmac_xof	4.550s	235.133us	5	5	100.00
V2	sideload	kmac_sideload	8.025m	71.393ms	50	50	100.00
V2	app	kmac_app	6.953m	67.734ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.665m	19.020ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.953m	30.791ms	50	50	100.00
V2	error	kmac_error	8.245m	14.806ms	50	50	100.00
V2	key_error	kmac_key_error	19.470s	11.950ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.450s	514.398us	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	39.050s	2.140ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	36.490s	6.402ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	57.510s	6.688ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	30.490s	1.644ms	50	50	100.00
V2	stress_all	kmac_stress_all	40.937m	30.365ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.380s	16.290us	50	50	100.00
V2	alert_test	kmac_alert_test	2.420s	263.998us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.720s	779.661us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.720s	779.661us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.800s	69.860us	5	5	100.00
		kmac_csr_rw	2.670s	93.953us	20	20	100.00
		kmac_csr_aliasing	10.020s	795.625us	5	5	100.00
		kmac_same_csr_outstanding	3.810s	92.833us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.800s	69.860us	5	5	100.00
		kmac_csr_rw	2.670s	93.953us	20	20	100.00
		kmac_csr_aliasing	10.020s	795.625us	5	5	100.00
		kmac_same_csr_outstanding	3.810s	92.833us	20	20	100.00
V2		TOTAL			740	740	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.380s	287.625us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.380s	287.625us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.380s	287.625us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.380s	287.625us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.480s	828.152us	14	20	70.00
V2S	tl_intg_err	kmac_sec_cm	1.573m	7.601ms	5	5	100.00
		kmac_tl_intg_err	5.980s	949.734us	18	20	90.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.980s	949.734us	18	20	90.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	30.490s	1.644ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.548m	5.085ms	48	50	96.00
V2S	sec_cm_key_sideload	kmac_sideload	8.025m	71.393ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.380s	287.625us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.573m	7.601ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.573m	7.601ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.573m	7.601ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.548m	5.085ms	48	50	96.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	30.490s	1.644ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.573m	7.601ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.165m	200.000ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.548m	5.085ms	48	50	96.00
V2S		TOTAL			66	75	88.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	3.300m	11.868ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			926	940	98.51

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.38	99.09	94.43	99.89	80.28	97.05	99.06	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 7 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

5.kmac_shadow_reg_errors_with_csr_rw.7757899429802062537653990205205451298188973896781181352401258905417702839148
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @  41725998 ps: (kmac_csr_assert_fpv.sv:537) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @  41725998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors_with_csr_rw.114617727647428172628851828390929651212607725433117381909060112882130449981138
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  10022632 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  10022632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test kmac_tl_intg_err has 2 failures.

7.kmac_tl_intg_err.20042086277499257784849921435547593542238721846276949893551824136148124315918
Line 82, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  43426609 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  43426609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.kmac_tl_intg_err.72874290651970910085261172727872223367110341166420451102092510793325185722122
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[39] & 'hffffffff)))'
  UVM_ERROR @   9835882 ps: (kmac_csr_assert_fpv.sv:492) [ASSERT FAILED] prefix_0_rd_A
  UVM_INFO @   9835882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 3.kmac_stress_all_with_rand_reset.72857030009905819661408855602860185908334731902600641952343927131578678487189
    Line 85, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 648022893 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 648022893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.kmac_stress_all_with_rand_reset.94498665151462684893708089675516032856988999317234017151827317446325880859300
    Line 147, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1773999675 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483768 [0x80000078]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1773999675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:

Test kmac_smoke has 2 failures.

10.kmac_smoke.48832537145184189827127140195407735695949753650174694757265071285906290934446
Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/10.kmac_smoke/latest/run.log

  UVM_ERROR @  35938882 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  35938882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.kmac_smoke.3624434671946373660108499273793856317760079508667128620271960332377149181662
Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/28.kmac_smoke/latest/run.log

  UVM_ERROR @ 187354984 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 187354984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_mubi has 1 failures.
  - 4.kmac_mubi.18515256653497816406618937879878702134692443293172276184210635805044673161661
    Line 230, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_mubi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 15.kmac_shadow_reg_errors_with_csr_rw.39230605277297396523355646293601033125197001596907497545592455892770619906006
    Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  54508600 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (2462037760 [0x92bfb700] vs 3731385264 [0xde686bb0]) Regname: kmac_reg_block.prefix_4 reset value: 0x0
  UVM_INFO @  54508600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```