KMAC/UNMASKED Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.050m	14.188ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.670s	46.364us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.610s	58.512us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.370s	964.068us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.980s	489.186us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.450s	36.047us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.610s	58.512us	20	20	100.00
		kmac_csr_aliasing	9.980s	489.186us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.210s	10.909us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.750s	174.630us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	40.566m	342.787ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.346m	259.516ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	36.948m	922.165ms	5	5	100.00
		kmac_test_vectors_sha3_256	30.980m	359.648ms	5	5	100.00
		kmac_test_vectors_sha3_384	16.018m	25.356ms	5	5	100.00
		kmac_test_vectors_sha3_512	18.780s	1.039ms	5	5	100.00
		kmac_test_vectors_shake_128	38.889m	449.878ms	5	5	100.00
		kmac_test_vectors_shake_256	25.711m	231.386ms	5	5	100.00
		kmac_test_vectors_kmac	3.980s	1.042ms	5	5	100.00
		kmac_test_vectors_kmac_xof	3.810s	160.966us	5	5	100.00
V2	sideload	kmac_sideload	6.372m	36.257ms	50	50	100.00
V2	app	kmac_app	4.714m	57.586ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	3.151m	10.544ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.506m	29.630ms	50	50	100.00
V2	error	kmac_error	7.043m	82.290ms	50	50	100.00
V2	key_error	kmac_key_error	26.290s	33.818ms	49	50	98.00
V2	sideload_invalid	kmac_sideload_invalid	2.659m	10.026ms	42	50	84.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.650s	1.926ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.870s	4.434ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	59.910s	15.969ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	28.960s	610.240us	50	50	100.00
V2	stress_all	kmac_stress_all	29.433m	143.664ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.360s	25.289us	50	50	100.00
V2	alert_test	kmac_alert_test	2.270s	52.864us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.390s	873.363us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.390s	873.363us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.670s	46.364us	5	5	100.00
		kmac_csr_rw	2.610s	58.512us	20	20	100.00
		kmac_csr_aliasing	9.980s	489.186us	5	5	100.00
		kmac_same_csr_outstanding	3.410s	167.009us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.670s	46.364us	5	5	100.00
		kmac_csr_rw	2.610s	58.512us	20	20	100.00
		kmac_csr_aliasing	9.980s	489.186us	5	5	100.00
		kmac_same_csr_outstanding	3.410s	167.009us	20	20	100.00
V2		TOTAL			731	740	98.78
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	3.180s	196.843us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	3.180s	196.843us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	3.180s	196.843us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	3.180s	196.843us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.830s	370.346us	11	20	55.00
V2S	tl_intg_err	kmac_sec_cm	41.770s	4.461ms	5	5	100.00
		kmac_tl_intg_err	5.060s	243.875us	15	20	75.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.060s	243.875us	15	20	75.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	28.960s	610.240us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.050m	14.188ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.372m	36.257ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	3.180s	196.843us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	41.770s	4.461ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	41.770s	4.461ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	41.770s	4.461ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.050m	14.188ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	28.960s	610.240us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	41.770s	4.461ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.964m	10.175ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.050m	14.188ms	50	50	100.00
V2S		TOTAL			61	75	81.33
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.808m	5.783ms	2	10	20.00
V3		TOTAL			2	10	20.00
		TOTAL			909	940	96.70

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.67	97.18	94.38	100.00	72.73	95.93	99.02	96.41

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 14 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 9 failures.

0.kmac_shadow_reg_errors_with_csr_rw.82323175301783431887944830378231564154939591950522784959694787242730126520294
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
  UVM_ERROR @  33776128 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
  UVM_INFO @  33776128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_shadow_reg_errors_with_csr_rw.88041874228748707385038101190821642456649084248458543025600426272384967456482
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  83195581 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  83195581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test kmac_tl_intg_err has 5 failures.

1.kmac_tl_intg_err.107113500046104284999640731143290531605120597298383455427927171668336852915652
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/1.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
  UVM_ERROR @  36962761 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
  UVM_INFO @  36962761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_tl_intg_err.7956095012718708471948034819847230407776064048936277690290586165717115317569
Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[47] & 'hffffffff)))'
  UVM_ERROR @  22816076 ps: (kmac_csr_assert_fpv.sv:532) [ASSERT FAILED] prefix_8_rd_A
  UVM_INFO @  22816076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (cip_base_vseq.sv:907) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 0.kmac_stress_all_with_rand_reset.24643660042805178799907411189802004342192628314933633701296554540330958011366
    Line 170, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14431796702 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 14431796702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.60868391924526617092353980760594196539032314469994255120502590616608921869785
    Line 196, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5782913574 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 5782913574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
- Test kmac_stress_all_with_rand_reset has 4 failures.
  - 2.kmac_stress_all_with_rand_reset.101517713243750352449247624772957708457294099499813112566407478705138651730472
    Line 103, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2317637616 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2317637616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.kmac_stress_all_with_rand_reset.37846536085013246487754032054542815573095193974486495215149572881781492213492
    Line 104, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1542336944 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 1542336944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 14.kmac_sideload_invalid.35624249685541084097137841123584085586421892248960395734228745931376069363159
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/14.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10091726315 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbf6b3000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10091726315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 37.kmac_sideload_invalid.62364186218014163591905449518237945214014151049479407077788473580458982127348
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/37.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10039589596 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xd500c000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10039589596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 17.kmac_sideload_invalid.53044474094343721803672577300205958783328953224191577317615522140819463400462
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/17.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10184652993 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4edd2000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10184652993 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 30.kmac_sideload_invalid.97594403390812216167165989791978321291263073015559279320976151307747177398978
    Line 83, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/30.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10373629316 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x55ae7000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10373629316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 4.kmac_sideload_invalid.40424697790220040243934723280831194449436329335790052308381504965171840633067
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/4.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10910285761 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbefbc000, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
  UVM_INFO @ 10910285761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 13.kmac_sideload_invalid.41672161943126232623141195644756696452554805851673274317995471995350610568787
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/13.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10236115518 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe6fdc000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10236115518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:382) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 15.kmac_key_error.1821891141142885448259134560297062985836739009387274603346224175741137994178
    Line 78, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/15.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 1279365380 ps: (kmac_base_vseq.sv:382) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 1279365380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 20.kmac_sideload_invalid.22850424396019520517895267872155125688862029012603538618302637413740982829572
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/20.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10025719643 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x91cc8000, Comparison=CompareOpEq, exp_data=0x1, call_count=6)
  UVM_INFO @ 10025719643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 46.kmac_sideload_invalid.70595993593708821689340106657096808819639032081221983800926677211638662551126
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/46.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10308708444 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x189c1000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10308708444 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```