OTBN Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	52.000s	438.465us	1	1	100.00
V1	single_binary	otbn_single	2.550m	1.936ms	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	9.000s	24.545us	5	5	100.00
V1	csr_rw	otbn_csr_rw	7.000s	40.078us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	8.000s	26.634us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	14.016us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	20.000s	96.574us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	7.000s	40.078us	20	20	100.00
		otbn_csr_aliasing	7.000s	14.016us	5	5	100.00
V1	mem_walk	otbn_mem_walk	31.000s	1.870ms	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	22.000s	1.707ms	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	1.117m	153.137us	10	10	100.00
V2	multi_error	otbn_multi_err	1.417m	1.489ms	1	1	100.00
V2	back_to_back	otbn_multi	1.767m	853.890us	10	10	100.00
V2	stress_all	otbn_stress_all	6.167m	2.262ms	9	10	90.00
V2	lc_escalation	otbn_escalate	2.067m	913.666us	58	60	96.67
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	15.000s	25.179us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	30.000s	85.246us	10	10	100.00
V2	alert_test	otbn_alert_test	10.000s	21.346us	50	50	100.00
V2	intr_test	otbn_intr_test	8.000s	29.239us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	10.000s	93.662us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	10.000s	93.662us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	9.000s	24.545us	5	5	100.00
		otbn_csr_rw	7.000s	40.078us	20	20	100.00
		otbn_csr_aliasing	7.000s	14.016us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	31.368us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	9.000s	24.545us	5	5	100.00
		otbn_csr_rw	7.000s	40.078us	20	20	100.00
		otbn_csr_aliasing	7.000s	14.016us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	31.368us	20	20	100.00
V2		TOTAL			243	246	98.78
V2S	mem_integrity	otbn_imem_err	34.000s	202.041us	10	10	100.00
		otbn_dmem_err	56.000s	34.771us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	32.000s	21.796us	5	5	100.00
		otbn_controller_ispr_rdata_err	27.000s	112.934us	5	5	100.00
		otbn_mac_bignum_acc_err	15.000s	315.777us	5	5	100.00
		otbn_urnd_err	10.000s	41.716us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	32.956us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	11.000s	18.401us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	12.000s	33.087us	8	10	80.00
V2S	tl_intg_err	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
		otbn_tl_intg_err	28.000s	274.563us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	42.000s	225.270us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	prim_count_check	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_mem_scramble	otbn_smoke	52.000s	438.465us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	56.000s	34.771us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	34.000s	202.041us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	28.000s	274.563us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	2.067m	913.666us	58	60	96.67
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	34.000s	202.041us	10	10	100.00
		otbn_dmem_err	56.000s	34.771us	15	15	100.00
		otbn_zero_state_err_urnd	15.000s	25.179us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	32.956us	5	5	100.00
		otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_scramble_key_sideload	otbn_single	2.550m	1.936ms	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	34.000s	202.041us	10	10	100.00
		otbn_dmem_err	56.000s	34.771us	15	15	100.00
		otbn_zero_state_err_urnd	15.000s	25.179us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	32.956us	5	5	100.00
		otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	2.067m	913.666us	58	60	96.67
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	34.000s	202.041us	10	10	100.00
		otbn_dmem_err	56.000s	34.771us	15	15	100.00
		otbn_zero_state_err_urnd	15.000s	25.179us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	32.956us	5	5	100.00
		otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	2.550m	1.936ms	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	14.000s	35.675us	10	12	83.33
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	26.000s	75.309us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	37.000s	469.567us	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	37.000s	469.567us	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	14.000s	23.393us	9	10	90.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	25.000s	142.985us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	1.967m	1.937ms	5	5	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	1.967m	1.937ms	5	5	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	10.000s	20.010us	6	7	85.71
V2S	sec_cm_data_mem_sec_wipe	otbn_single	2.550m	1.936ms	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	2.550m	1.936ms	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	2.550m	1.936ms	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.767m	853.890us	10	10	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	2.550m	1.936ms	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	2.550m	1.936ms	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	13.000s	25.416us	5	5	100.00
V2S	sec_cm_key_sideload	otbn_single	2.550m	1.936ms	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.483m	2.182ms	4	5	80.00
V2S		TOTAL			153	163	93.87
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.400m	2.370ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			567	585	96.92

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.11	99.64	96.06	99.73	93.17	93.54	100.00	97.72	100.00

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_ctrl_redun has 2 failures.

0.otbn_ctrl_redun.8013501866349190333978780777085352638107433312391991884793025334891062594568
Line 112, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 15672087 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  15672087 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  15672087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.otbn_ctrl_redun.12758613196590831369060845871067956299494505218261077846223061408732164523355
Line 113, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_ctrl_redun/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 21588029 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 21588029 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @  21588029 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  21588029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_sec_wipe_err has 1 failures.

5.otbn_sec_wipe_err.90370819659163476647274347908384693920600261089345817381059450790392478693454
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 16796456 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  16796456 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  16796456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

25.otbn_escalate.84266392623115491542106489623432978164939020003974799142074806354447320104532
Line 116, in log /nightly/runs/scratch/master/otbn-sim-xcelium/25.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 52186864 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  52186864 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  52186864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:908) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 0.otbn_stress_all_with_rand_reset.9017270005085073161573077939730615310132208854269693279528472847110725865160
    Line 196, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2783090138 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2783090138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.otbn_stress_all_with_rand_reset.14583056491482273676374935415843968577763508278877280274694506067724723068034
    Line 154, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 120710072 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 120710072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 3 failures:

Test otbn_stress_all_with_rand_reset has 1 failures.

6.otbn_stress_all_with_rand_reset.6744696983936982091594503853715213360326584327511338523379776637668871085677
Line 164, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 252721065 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 252721065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stress_all has 1 failures.

9.otbn_stress_all.83596190600451842379331143254635699465422313515054270538836390329292757630366
Line 238, in log /nightly/runs/scratch/master/otbn-sim-xcelium/9.otbn_stress_all/latest/run.log

  UVM_FATAL @ 541334070 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 541334070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

16.otbn_escalate.108723996148140134430288149600933597841307286518741953959524761407592471276349
Line 106, in log /nightly/runs/scratch/master/otbn-sim-xcelium/16.otbn_escalate/latest/run.log

  UVM_FATAL @  73881603 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  73881603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 3 failures:
- Test otbn_passthru_mem_tl_intg_err has 3 failures.
  - 6.otbn_passthru_mem_tl_intg_err.47909269071873999545802110440445962445221291371789867178452127976924712757405
    Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  10699473 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  10699473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.otbn_passthru_mem_tl_intg_err.18823766889598780297872074215130259184459021467594389834417536422939877976297
    Line 92, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  74662753 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  74662753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 3.otbn_stress_all_with_rand_reset.12669149817197943663779120342439122703553792333985315418931618956059887269476
    Line 155, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  17194148 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  17194148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,171): Assertion NotRunningWhenLocked_A has failed has 1 failures:

Test otbn_partial_wipe has 1 failures.

3.otbn_partial_wipe.17217301185077310801929410247964314027380254131327307945299279714923872222251
Line 100, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_partial_wipe/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sva_0.1/otbn_idle_checker.sv,171): (time 11553859 PS) Assertion tb.dut.idle_checker.NotRunningWhenLocked_A has failed
  UVM_ERROR @  11553859 ps: (otbn_idle_checker.sv:171) [ASSERT FAILED] NotRunningWhenLocked_A
  UVM_INFO @  11553859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 1 failures:

Test otbn_sec_cm has 1 failures.

3.otbn_sec_cm.85506611972181103494851003253623563967967728329894443790855313731833268917031
Line 91, in log /nightly/runs/scratch/master/otbn-sim-xcelium/3.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 44625426 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 44625426 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  44625426 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  44625426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:

Test otbn_rf_base_intg_err has 1 failures.

5.otbn_rf_base_intg_err.73925090576483003919328743377772612722154090203884746414709464271790869233472
Line 108, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_rf_base_intg_err/latest/run.log

  UVM_ERROR @  34317557 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.otbn_rf_base_intg_err_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  34317557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 6.otbn_partial_wipe.17725355630140273857875683362695844061505139781173906024029715164660662441075
    Line 104, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 8282625 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   8282625 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   8282625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```