5d515c3| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 9.000s | 126.527us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 47.745us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 4.000s | 22.262us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 132.388us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 53.800us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 489.523us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 4.000s | 22.262us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 53.800us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 1.483m | 5.311ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.367m | 10.114ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 5.000s | 37.725us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 3.033m | 10.867ms | 26 | 50 | 52.00 |
| V2 | alert_test | pattgen_alert_test | 5.000s | 117.969us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 12.976us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 7.000s | 472.239us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 7.000s | 472.239us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 47.745us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 4.000s | 22.262us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 53.800us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 6.000s | 15.589us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 47.745us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 4.000s | 22.262us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 53.800us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 6.000s | 15.589us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 316 | 340 | 92.94 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 5.000s | 197.703us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 5.000s | 154.964us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 5.000s | 197.703us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.217m | 29.156ms | 3 | 50 | 6.00 |
| V3 | TOTAL | 3 | 50 | 6.00 | |||
| Unmapped tests | pattgen_inactive_level | 1.467m | 10.031ms | 41 | 50 | 82.00 | |
| TOTAL | 490 | 570 | 85.96 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.89 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 90.73 |
UVM_ERROR (cip_base_vseq.sv:908) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:
0.pattgen_stress_all_with_rand_reset.94437926390200076333163991608673682793828713651281631870730477257103311493340
Line 160, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1579573820 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1579585234 ps: (cip_base_vseq.sv:812) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1579585234 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/5
UVM_INFO @ 1579905234 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.44855400836952483570824170603874448002332987739751188904211796843515341380292
Line 170, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3152697613 ps: (cip_base_vseq.sv:908) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 3152708746 ps: (cip_base_vseq.sv:812) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3152708746 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 3152788746 ps: (cip_base_vseq.sv:836) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 44 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 24 failures:
0.pattgen_stress_all.63278559270172442256827991544813223808207411032204441074635288089357387883317
Line 158, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 10154875805 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10962
2.pattgen_stress_all.6448564835834014683710302727405700077791275233311269126426967088370920688389
Line 150, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_stress_all/latest/run.log
UVM_ERROR @ 2732958349 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11987
... and 22 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
1.pattgen_inactive_level.60361349067566569277596298332253469515123036553224615019819301344784534544421
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10039190802 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xeca376d0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10039190802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
2.pattgen_inactive_level.48358221781351044445378630982669413826507402658854561699538104514249927427143
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10005493250 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x63292cd0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10005493250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=28) has 1 failures:
7.pattgen_inactive_level.103913432356470850842351979390936858644771205540077948507998142531663271489165
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10086718514 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xf3be5d90, Comparison=CompareOpEq, exp_data=0x0, call_count=28)
UVM_INFO @ 10086718514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
19.pattgen_inactive_level.56904587427988299631844962138525390737425672832685047383754461040248076447247
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10030822882 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe30d0e90, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10030822882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
19.pattgen_stress_all_with_rand_reset.11287925840671739657396524017084487616912764612466922120125930036083126881665
Line 125, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 369553642 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
21.pattgen_inactive_level.37065690811155098281097453090262024107575330392466461711911699200823761742365
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10025519621 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa5858cd0, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10025519621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
24.pattgen_inactive_level.30425183193964711673583851511745262682809484834979081308524039097514470430531
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10032049964 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8c6d6150, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10032049964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
42.pattgen_inactive_level.924113169960823119470110987827075840229402589758968407428851104306958811376
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10278494260 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x1c306950, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
UVM_INFO @ 10278494260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
46.pattgen_inactive_level.100288118858677399418973726521989463729356502629230140472930628842461166343997
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10102653907 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb39ea010, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
UVM_INFO @ 10102653907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
49.pattgen_inactive_level.80705847002558455188103364461804488267435757737323047503787770668273304616886
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10179677072 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x72e66d50, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
UVM_INFO @ 10179677072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---