PRIM_ESC Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	prim_esc_request_test	prim_esc_test	1.740s	5.386us	20	20	100.00
V1	prim_ping_req_interrupted_by_esc_req_test	prim_esc_test	1.740s	5.386us	20	20	100.00
V1	prim_esc_tx_integrity_errors_test	prim_esc_test	1.740s	5.386us	20	20	100.00
V1	prim_esc_reverse_ping_timeout_test	prim_esc_test	1.740s	5.386us	20	20	100.00
V1	prim_esc_receiver_counter_fail_test	prim_esc_test	1.740s	5.386us	20	20	100.00
V1	prim_esc_handshake_with_rand_reset_test	prim_esc_test	1.740s	5.386us	20	20	100.00
V1		TOTAL			20	20	100.00
		TOTAL			20	20	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.29	95.41	87.80	100.00	96.43	88.89	85.19