ROM_CTRL/32KB Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.450s	184.527us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	8.390s	314.807us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	7.910s	2.286ms	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	7.870s	168.894us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	6.810s	551.408us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	10.400s	550.808us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	7.910s	2.286ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.810s	551.408us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	7.230s	1.068ms	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	7.260s	167.040us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	8.290s	184.762us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	25.500s	1.953ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	11.320s	547.585us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	9.510s	547.646us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	12.700s	530.180us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	12.700s	530.180us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	8.390s	314.807us	5	5	100.00
		rom_ctrl_csr_rw	7.910s	2.286ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.810s	551.408us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.050s	540.263us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	8.390s	314.807us	5	5	100.00
		rom_ctrl_csr_rw	7.910s	2.286ms	20	20	100.00
		rom_ctrl_csr_aliasing	6.810s	551.408us	5	5	100.00
		rom_ctrl_same_csr_outstanding	10.050s	540.263us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	34.480s	6.253ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.927m	996.927us	5	5	100.00
		rom_ctrl_tl_intg_err	1.138m	734.197us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.927m	996.927us	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.927m	996.927us	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.927m	996.927us	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.927m	996.927us	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.450s	184.527us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.450s	184.527us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.450s	184.527us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	1.138m	734.197us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
		rom_ctrl_kmac_err_chk	11.320s	547.585us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	2.994m	5.259ms	16	20	80.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	34.480s	6.253ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.927m	996.927us	5	5	100.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	7.398m	5.131ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			262	266	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.41	99.87	98.68	100.00	100.00	99.29	98.97	99.05

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.69644610692846110200716472791114078477743631881199950225696067948236541136521
      Line 89, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1684873836 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1684873836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.rom_ctrl_corrupt_sig_fatal_chk.25795509245550055308490488966979196613546517850560028722924368822416343786936
      Line 84, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 932109553 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:324) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 932109553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.