RV_TIMER Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	31.104m	553.511ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.090s	17.692us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.260s	15.210us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5.190s	709.289us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.310s	35.103us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.990s	370.383us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.260s	15.210us	20	20	100.00
		rv_timer_csr_aliasing	2.310s	35.103us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	10.661m	529.476ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.212m	201.613ms	50	50	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	19.499m	2.603s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	19.499m	2.603s	50	50	100.00
V2	stress	rv_timer_stress_all	55.540m	1.002s	49	50	98.00
V2	intr_test	rv_timer_intr_test	2.310s	30.538us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.980s	1.017ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.980s	1.017ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.090s	17.692us	5	5	100.00
		rv_timer_csr_rw	2.260s	15.210us	20	20	100.00
		rv_timer_csr_aliasing	2.310s	35.103us	5	5	100.00
		rv_timer_same_csr_outstanding	2.420s	32.333us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.090s	17.692us	5	5	100.00
		rv_timer_csr_rw	2.260s	15.210us	20	20	100.00
		rv_timer_csr_aliasing	2.310s	35.103us	5	5	100.00
		rv_timer_same_csr_outstanding	2.420s	32.333us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	rv_timer_sec_cm	2.490s	181.323us	5	5	100.00
		rv_timer_tl_intg_err	3.070s	105.859us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.070s	105.859us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.624m	24.617ms	11	50	22.00
V3		TOTAL			11	50	22.00
		TOTAL			580	620	93.55

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.19	99.65	99.08	92.06	--	99.13	99.68	99.54

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:907) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 38 failures:

  • Test rv_timer_stress_all_with_rand_reset has 38 failures.

    • 0.rv_timer_stress_all_with_rand_reset.19355870091147636778157788957806288700481502292179984803448378113513619028605
      Line 207, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 9586046180 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10012 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 9586046180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_timer_stress_all_with_rand_reset.42392915421037130849765563449222634507903102592357731446509105555096558750280
      Line 91, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 556240944 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 556240944 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 36 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test rv_timer_stress_all has 1 failures.

    • 14.rv_timer_stress_all.91193597317603641374111103420103065138559252930011862987062256914935743700900
      Line 110, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/14.rv_timer_stress_all/latest/run.log

        UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:811) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:

  • Test rv_timer_stress_all_with_rand_reset has 1 failures.

    • 32.rv_timer_stress_all_with_rand_reset.111264336553297406427470268778123755464647993528690569675703508368272240902404
      Line 161, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/32.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3910350741 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 3910350741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---