SPI_DEVICE/1R1W Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.885m	73.894ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.750s	29.532us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.220s	119.434us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	30.870s	2.814ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	19.850s	1.371ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.190s	169.581us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.220s	119.434us	20	20	100.00
		spi_device_csr_aliasing	19.850s	1.371ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.210s	26.715us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.860s	68.514us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.340s	64.763us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.250s	1.470us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	1.940s	1.424us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	10.180s	310.371us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	10.180s	310.371us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	37.830s	9.330ms	50	50	100.00
		spi_device_tpm_sts_read	2.680s	116.496us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	38.740s	29.879ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	28.360s	26.741ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.500s	51.661ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.500s	51.661ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	22.640s	3.348ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	22.640s	3.348ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	22.640s	3.348ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	22.640s	3.348ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	22.640s	3.348ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	48.830s	22.677ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.385m	44.553ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.385m	44.553ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.385m	44.553ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.681m	40.391ms	50	50	100.00
		spi_device_read_buffer_direct	18.530s	8.214ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.385m	44.553ms	50	50	100.00
		spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.801m	133.109ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	21.810s	11.402ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	21.810s	11.402ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.885m	73.894ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.355m	290.732ms	50	50	100.00
V2	stress_all	spi_device_stress_all	12.682m	328.758ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.320s	99.929us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.360s	24.255us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.840s	375.663us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.840s	375.663us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.750s	29.532us	5	5	100.00
		spi_device_csr_rw	4.220s	119.434us	20	20	100.00
		spi_device_csr_aliasing	19.850s	1.371ms	5	5	100.00
		spi_device_same_csr_outstanding	6.260s	164.662us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.750s	29.532us	5	5	100.00
		spi_device_csr_rw	4.220s	119.434us	20	20	100.00
		spi_device_csr_aliasing	19.850s	1.371ms	5	5	100.00
		spi_device_same_csr_outstanding	6.260s	164.662us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.870s	98.644us	5	5	100.00
		spi_device_tl_intg_err	19.200s	1.658ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	19.200s	1.658ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	6.304m	64.767ms	50	50	100.00
		TOTAL			1130	1151	98.18

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.44	98.98	96.22	83.25	89.36	98.37	95.66	99.21

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*])

has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.66527135258841384873904327140044316795016835105715413603852085918177279624773
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   2066828 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[107])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   2066828 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   2066828 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1003])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.12864998477470329544586162749765250521317335601147362103926962679942229651895
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4721891 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[107])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4721891 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4721891 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[1003])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.42013030279713787373464527646356599939328726419468781904264763525461087313724
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    757089 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    757089 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
  UVM_ERROR @    781089 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4547a7 [10001010100011110100111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
  UVM_ERROR @    781089 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0x4547a7 [10001010100011110100111] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])