SPI_DEVICE/2P Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.166m	76.221ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.740s	150.553us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.370s	1.559ms	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.190s	38.672ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	20.360s	5.042ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.440s	147.482us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.370s	1.559ms	20	20	100.00
		spi_device_csr_aliasing	20.360s	5.042ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.290s	19.906us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.820s	58.538us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.500s	19.790us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.670s	32.918us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.700s	2.187us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	6.990s	1.233ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	6.990s	1.233ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	21.290s	37.299ms	50	50	100.00
		spi_device_tpm_sts_read	2.670s	361.702us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	44.050s	26.467ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	32.070s	13.423ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	30.340s	15.405ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	30.340s	15.405ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	26.750s	2.756ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	26.750s	2.756ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	26.750s	2.756ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	26.750s	2.756ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	26.750s	2.756ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	38.650s	50.558ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.759m	91.826ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.759m	91.826ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.759m	91.826ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	41.620s	10.766ms	50	50	100.00
		spi_device_read_buffer_direct	22.890s	3.949ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.759m	91.826ms	50	50	100.00
		spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	6.136m	76.017ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	22.910s	2.981ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	22.910s	2.981ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.166m	76.221ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	5.375m	40.890ms	50	50	100.00
V2	stress_all	spi_device_stress_all	17.959m	648.009ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.370s	231.039us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.400s	39.537us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.330s	191.749us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.330s	191.749us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.740s	150.553us	5	5	100.00
		spi_device_csr_rw	4.370s	1.559ms	20	20	100.00
		spi_device_csr_aliasing	20.360s	5.042ms	5	5	100.00
		spi_device_same_csr_outstanding	5.690s	60.534us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.740s	150.553us	5	5	100.00
		spi_device_csr_rw	4.370s	1.559ms	20	20	100.00
		spi_device_csr_aliasing	20.360s	5.042ms	5	5	100.00
		spi_device_same_csr_outstanding	5.690s	60.534us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	3.050s	115.850us	5	5	100.00
		spi_device_tl_intg_err	22.240s	993.059us	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	22.240s	993.059us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	3.901m	254.832ms	50	50	100.00
		TOTAL			1150	1151	99.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.47	99.02	96.31	83.25	89.36	98.48	95.65	99.26

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.13078557324346372013467573012157524859444396394645891364650453588412019498340
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1406134 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1406134 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   1457134 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x875e61 [100001110101111001100001] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   1457134 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)