SPI_HOST Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: `5d515c3`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	6.333m	51.434ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	20.757us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	19.395us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	324.412us	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	92.489us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	63.521us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	19.395us	20	20	100.00
		spi_host_csr_aliasing	4.000s	92.489us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	141.470us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	23.727us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	90.628us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	2.317m	14.024ms	50	50	100.00
		spi_host_error_cmd	5.000s	50.517us	50	50	100.00
		spi_host_event	13.633m	29.066ms	50	50	100.00
V2	clock_rate	spi_host_speed	31.000s	766.334us	50	50	100.00
V2	speed	spi_host_speed	31.000s	766.334us	50	50	100.00
V2	chip_select_timing	spi_host_speed	31.000s	766.334us	50	50	100.00
V2	sw_reset	spi_host_sw_reset	2.183m	4.405ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	467.476us	50	50	100.00
V2	cpol_cpha	spi_host_speed	31.000s	766.334us	50	50	100.00
V2	full_cycle	spi_host_speed	31.000s	766.334us	50	50	100.00
V2	duplex	spi_host_smoke	6.333m	51.434ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	6.333m	51.434ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.800m	13.987ms	50	50	100.00
V2	spien	spi_host_spien	2.133m	4.141ms	50	50	100.00
V2	stall	spi_host_status_stall	5.933m	13.781ms	43	50	86.00
V2	Idlecsbactive	spi_host_idlecsbactive	27.000s	2.062ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	2.317m	14.024ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	19.424us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	24.432us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	9.000s	261.883us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	9.000s	261.883us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	20.757us	5	5	100.00
		spi_host_csr_rw	5.000s	19.395us	20	20	100.00
		spi_host_csr_aliasing	4.000s	92.489us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	16.773us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	20.757us	5	5	100.00
		spi_host_csr_rw	5.000s	19.395us	20	20	100.00
		spi_host_csr_aliasing	4.000s	92.489us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	16.773us	20	20	100.00
V2		TOTAL			682	690	98.84
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	61.059us	20	20	100.00
		spi_host_sec_cm	5.000s	66.587us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	61.059us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	51.300m	100.001ms	2	10	20.00
		TOTAL			824	840	98.10

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.28	96.74	93.21	98.70	94.71	88.02	100.00	96.86	91.56

Failure Buckets

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 5 failures:
- Test spi_host_upper_range_clkdiv has 5 failures.
  - 0.spi_host_upper_range_clkdiv.103553983790450987208370664360165307927251256566493936090364434599768518027187
    Line 113, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100003065719 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x900e8dd4, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100003065719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.spi_host_upper_range_clkdiv.92969544984249290968046651395562464476249409455185496544113760484868123978957
    Line 159, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100001764258 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x3747a94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 100001764258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
- Test spi_host_upper_range_clkdiv has 2 failures.
  - 3.spi_host_upper_range_clkdiv.8694122325343137582529880413776107673205180746473110254075075918026212896812
    Line 138, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100011241941 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xcf6c6494, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 100011241941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.spi_host_upper_range_clkdiv.1110459395340223470785523301372849449733978028444967113685091994418818689945
    Line 139, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/6.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 100005805813 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.active (addr=0xde4e6094, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 100005805813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 2 failures:

Test spi_host_status_stall has 2 failures.

3.spi_host_status_stall.17318084282348158423602321465184115837786575615464143869161173837873057255264
Line 776, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 314945510 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 314945510 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=314946000 ps
  UVM_INFO @ 314945510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.spi_host_status_stall.10329302137548910270901420932363272103669272623754225502552288310205456989235
Line 706, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/47.spi_host_status_stall/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 355774351 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
  UVM_ERROR @ 355774351 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x1) != neg_value (0x1) - time=355774000 ps
  UVM_INFO @ 355774351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test spi_host_upper_range_clkdiv has 1 failures.
  - 1.spi_host_upper_range_clkdiv.92653092144001833030255296876876178276695109481498808371810801965284145834510
    Line 206, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=56) has 1 failures:
- Test spi_host_sw_reset has 1 failures.
  - 18.spi_host_sw_reset.105379466168566915531866244737225499949148587610531326227761366225731021332896
    Line 354, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/18.spi_host_sw_reset/latest/run.log
```
  UVM_FATAL @ 10088931013 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x413c9194, Comparison=CompareOpEq, exp_data=0x0, call_count=56)
  UVM_INFO @ 10088931013 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=85) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 18.spi_host_status_stall.104606849315022779339683035306184043336381516849819555930613825760797880321332
    Line 725, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/18.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 11039359448 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x62c10014, Comparison=CompareOpEq, exp_data=0x1, call_count=85)
  UVM_INFO @ 11039359448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=90) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 21.spi_host_status_stall.14138035519726596869151707011037096565189390752062091312747665890374442845698
    Line 744, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/21.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 25396698868 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x2ce308d4, Comparison=CompareOpEq, exp_data=0x1, call_count=90)
  UVM_INFO @ 25396698868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=75) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 27.spi_host_status_stall.30331784905029251716573437082859529827513081089443366390550676529279237878610
    Line 651, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/27.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 25059843526 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xa4bfe454, Comparison=CompareOpEq, exp_data=0x1, call_count=75)
  UVM_INFO @ 25059843526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=81) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 43.spi_host_status_stall.45077443359089992948695415961100055657428282166515926670767644740478838861565
    Line 709, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/43.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 10079688911 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x82c35bd4, Comparison=CompareOpEq, exp_data=0x1, call_count=81)
  UVM_INFO @ 10079688911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=93) has 1 failures:
- Test spi_host_status_stall has 1 failures.
  - 46.spi_host_status_stall.68345431253546264000717486989709954950907862492512890653302030840556620266380
    Line 767, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/46.spi_host_status_stall/latest/run.log
```
  UVM_FATAL @ 21137184483 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x85626994, Comparison=CompareOpEq, exp_data=0x1, call_count=93)
  UVM_INFO @ 21137184483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```