SRAM_CTRL/MAIN Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.678m	8.649ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.110s	47.866us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.220s	15.718us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.130s	98.053us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.110s	17.500us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.450s	364.066us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.220s	15.718us	20	20	100.00
		sram_ctrl_csr_aliasing	2.110s	17.500us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.567m	74.875ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	2.850m	19.532ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	21.878m	11.269ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.461m	19.862ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	43.233m	116.200ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	20.965m	108.379ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	1.862m	19.056ms	50	50	100.00
V2	executable	sram_ctrl_executable	22.091m	66.494ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.675m	4.256ms	50	50	100.00
		sram_ctrl_partial_access_b2b	9.529m	87.268ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.799m	1.593ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.581m	1.593ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.955m	955.676us	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.777m	27.620ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.890s	708.302us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.250h	761.412ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.170s	42.427us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	6.270s	508.685us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	6.270s	508.685us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.110s	47.866us	5	5	100.00
		sram_ctrl_csr_rw	2.220s	15.718us	20	20	100.00
		sram_ctrl_csr_aliasing	2.110s	17.500us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.370s	20.923us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.110s	47.866us	5	5	100.00
		sram_ctrl_csr_rw	2.220s	15.718us	20	20	100.00
		sram_ctrl_csr_aliasing	2.110s	17.500us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.370s	20.923us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.174m	29.396ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.270s	29.805us	0	5	0.00
		sram_ctrl_tl_intg_err	4.360s	226.269us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.270s	29.805us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.360s	226.269us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.777m	27.620ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.777m	27.620ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.220s	15.718us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	22.091m	66.494ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	22.091m	66.494ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	22.091m	66.494ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	1.862m	19.056ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.930s	3.504ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.174m	29.396ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	15.320s	13.321ms	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.678m	8.649ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.678m	8.649ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	22.091m	66.494ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.270s	29.805us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	1.862m	19.056ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.270s	29.805us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.270s	29.805us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.678m	8.649ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.270s	29.805us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.522m	35.230ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1169	1190	98.24

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	99.29	93.01	85.18	100.00	98.07	98.59	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:

  • Test sram_ctrl_readback_err has 10 failures.

    • 5.sram_ctrl_readback_err.51708476321679890328257392121424222281550234102394991553875309691028643541911
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 1314373419 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x29) != exp (0x5c)
        UVM_INFO @ 1314373419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 6.sram_ctrl_readback_err.40139786145231535505738787489344649982556794374658714069200490550335993559905
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/6.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2631404093 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x4) != exp (0x7d)
        UVM_INFO @ 2631404093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 8 more failures.

• Offending 'reqfifo_rvalid' has 6 failures:

  • Test sram_ctrl_mubi_enc_err has 6 failures.

    • 8.sram_ctrl_mubi_enc_err.53534418073006454505895951550306194760974610934694187474960659243194226982516
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 2737854448 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 2737854448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 10.sram_ctrl_mubi_enc_err.59446558243134851420875118810533015755238267197782829228487876449000810557769
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/10.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 697364660 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 697364660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 2.sram_ctrl_sec_cm.64564048380326942480647223948651290644880628045620711059159471246111952782738
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   3015480 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   3015480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.sram_ctrl_sec_cm.91808499403332437286118524190859913921213609520721391280356488543712240649403
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1999876 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1999876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.36786801232922142349298472168362735158509930821994401251794329442822891923492
      Line 97, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  12302320 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  12302320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.97493865863998819756261927325882342387511346271573471575803755407652148943083
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @  36245523 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @  36245523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---