SRAM_CTRL/RET Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.756m	773.761us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.970s	41.833us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.110s	21.081us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.000s	678.503us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.010s	34.813us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.610s	45.573us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.110s	21.081us	20	20	100.00
		sram_ctrl_csr_aliasing	2.010s	34.813us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	15.280s	2.752ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	7.770s	189.498us	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	26.435m	15.414ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.794m	4.488ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.476m	34.823ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	18.297m	4.374ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	14.430s	10.376ms	50	50	100.00
V2	executable	sram_ctrl_executable	19.078m	157.230ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.644m	810.270us	50	50	100.00
		sram_ctrl_partial_access_b2b	10.628m	114.179ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.651m	271.256us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.690m	593.228us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.718m	598.871us	50	50	100.00
V2	regwen	sram_ctrl_regwen	19.575m	69.014ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	2.360s	28.740us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.518h	71.443ms	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.200s	193.666us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.350s	175.089us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.350s	175.089us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.970s	41.833us	5	5	100.00
		sram_ctrl_csr_rw	2.110s	21.081us	20	20	100.00
		sram_ctrl_csr_aliasing	2.010s	34.813us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.200s	33.978us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.970s	41.833us	5	5	100.00
		sram_ctrl_csr_rw	2.110s	21.081us	20	20	100.00
		sram_ctrl_csr_aliasing	2.010s	34.813us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.200s	33.978us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	4.160s	1.816ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.120s	8.112us	0	5	0.00
		sram_ctrl_tl_intg_err	3.970s	685.835us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.120s	8.112us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.970s	685.835us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	19.575m	69.014ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	19.575m	69.014ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.110s	21.081us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	19.078m	157.230ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	19.078m	157.230ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	19.078m	157.230ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	14.430s	10.376ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	2.700s	611.762us	43	50	86.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	4.160s	1.816ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.760s	194.024us	43	50	86.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.756m	773.761us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.756m	773.761us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	19.078m	157.230ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.120s	8.112us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	14.430s	10.376ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.120s	8.112us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.120s	8.112us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.756m	773.761us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.120s	8.112us	0	5	0.00
V2S		TOTAL			126	145	86.90
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	12.978m	4.175ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1171	1190	98.40

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.27	93.01	85.10	100.00	98.03	98.58	98.33

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 7 failures:

  • Test sram_ctrl_readback_err has 7 failures.

    • 1.sram_ctrl_readback_err.23624288593478038299253536935749542920705117363472098980617576555354859793930
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  28022572 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x61) != exp (0x62)
        UVM_INFO @  28022572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 7.sram_ctrl_readback_err.107237502864296415908375557309284852445629183540320992168948019741969789943543
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/7.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  23031783 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x3b) != exp (0x63)
        UVM_INFO @  23031783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• Offending 'reqfifo_rvalid' has 7 failures:

  • Test sram_ctrl_mubi_enc_err has 7 failures.

    • 1.sram_ctrl_mubi_enc_err.77943036792260073455735843226192929618515405975213774058719972694589291190212
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @  55867982 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @  55867982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 22.sram_ctrl_mubi_enc_err.7873863389680326636198524736439779762196000476279874710991075459848067475329
      Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/22.sram_ctrl_mubi_enc_err/latest/run.log

            Offending 'reqfifo_rvalid'
        UVM_ERROR @ 257075121 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
        UVM_INFO @ 257075121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 5 more failures.

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:

  • Test sram_ctrl_sec_cm has 3 failures.

    • 0.sram_ctrl_sec_cm.33833895908435309191396887298614275621344508155614471135492110004759994546712
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8112189 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8112189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 2.sram_ctrl_sec_cm.5504672870717854878474835031264519568415545405351649449189841757621206534348
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   2539589 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   2539589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 1 more failures.

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 1.sram_ctrl_sec_cm.8405326624308090452550609734552351440448315473154460661838915968853351923751
      Line 96, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  10650575 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  10650575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 4.sram_ctrl_sec_cm.57247172815975996210497062462075493245633687342750946683016158584967071496973
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/4.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @  14516950 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @  14516950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---