UART Simulation Results

Sunday April 13 2025 00:09:53 UTC

GitHub Revision: 5d515c3

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.520s	11.618ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.280s	45.022us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.330s	15.188us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.860s	4.927ms	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.520s	16.526us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.670s	20.772us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.330s	15.188us	20	20	100.00
		uart_csr_aliasing	2.520s	16.526us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	5.584m	110.204ms	50	50	100.00
V2	parity	uart_smoke	38.520s	11.618ms	50	50	100.00
		uart_tx_rx	5.584m	110.204ms	50	50	100.00
V2	parity_error	uart_intr	8.097m	275.641ms	50	50	100.00
		uart_rx_parity_err	6.901m	207.653ms	50	50	100.00
V2	watermark	uart_tx_rx	5.584m	110.204ms	50	50	100.00
		uart_intr	8.097m	275.641ms	50	50	100.00
V2	fifo_full	uart_fifo_full	4.605m	113.855ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	3.889m	109.129ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	11.559m	250.765ms	300	300	100.00
V2	rx_frame_err	uart_intr	8.097m	275.641ms	50	50	100.00
V2	rx_break_err	uart_intr	8.097m	275.641ms	50	50	100.00
V2	rx_timeout	uart_intr	8.097m	275.641ms	50	50	100.00
V2	perf	uart_perf	24.059m	30.758ms	50	50	100.00
V2	sys_loopback	uart_loopback	26.360s	11.306ms	50	50	100.00
V2	line_loopback	uart_loopback	26.360s	11.306ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	4.994m	142.749ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.940m	65.901ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	22.710s	6.903ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	58.250s	6.298ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	17.194m	163.607ms	49	50	98.00
V2	stress_all	uart_stress_all	31.378m	254.150ms	50	50	100.00
V2	alert_test	uart_alert_test	2.170s	13.724us	50	50	100.00
V2	intr_test	uart_intr_test	2.350s	105.572us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	3.600s	211.819us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	3.600s	211.819us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.280s	45.022us	5	5	100.00
		uart_csr_rw	2.330s	15.188us	20	20	100.00
		uart_csr_aliasing	2.520s	16.526us	5	5	100.00
		uart_same_csr_outstanding	2.490s	96.836us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.280s	45.022us	5	5	100.00
		uart_csr_rw	2.330s	15.188us	20	20	100.00
		uart_csr_aliasing	2.520s	16.526us	5	5	100.00
		uart_same_csr_outstanding	2.490s	96.836us	20	20	100.00
V2		TOTAL			1089	1090	99.91
V2S	tl_intg_err	uart_sec_cm	2.620s	174.529us	5	5	100.00
		uart_tl_intg_err	3.190s	123.362us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	3.190s	123.362us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	2.309m	23.658ms	98	100	98.00
V3		TOTAL			98	100	98.00
		TOTAL			1317	1320	99.77

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.76	99.17	98.25	91.55	--	98.15	100.00	99.46

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:447) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: TxEmpty has 2 failures:

  • Test uart_long_xfer_wo_dly has 1 failures.

    • 0.uart_long_xfer_wo_dly.23367311695251059788309494335254750397560444570514644696974880923814605113445
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_long_xfer_wo_dly/latest/run.log

        UVM_ERROR @   1290999 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_ERROR @   1290999 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxWatermark
        UVM_INFO @ 25749064201 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 1/7
        UVM_INFO @ 29289582668 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 2/7
        UVM_INFO @ 36720526357 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_long_xfer_wo_dly_vseq] finished run 3/7
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 38.uart_stress_all_with_rand_reset.85716598263121510326991480369727265128807724218667857358027165181259675055757
      Line 122, in log /nightly/runs/scratch/master/uart-sim-vcs/38.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6057057952 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: TxEmpty
        UVM_INFO @ 6480394672 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/112
        UVM_INFO @ 6568928577 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 5/10
        UVM_INFO @ 6569303580 ps: (cip_base_vseq.sv:835) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
      

• UVM_ERROR (cip_base_vseq.sv:907) [uart_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 2.uart_stress_all_with_rand_reset.73211328265759065870128521053316679755836149493895628438582840884038740424523
      Line 103, in log /nightly/runs/scratch/master/uart-sim-vcs/2.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1950162199 ps: (cip_base_vseq.sv:907) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 1950166611 ps: (cip_base_vseq.sv:811) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 1950166611 ps: (cip_base_vseq.sv:815) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 2/5
        UVM_INFO @ 1950172616 ps: (uart_intr_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_intr_vseq] finished run 1/1