ADC_CTRL Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	adc_ctrl_smoke	22.810s	5.986ms	50	50	100.00
V1	csr_hw_reset	adc_ctrl_csr_hw_reset	4.490s	1.240ms	5	5	100.00
V1	csr_rw	adc_ctrl_csr_rw	3.500s	468.632us	20	20	100.00
V1	csr_bit_bash	adc_ctrl_csr_bit_bash	56.100s	51.737ms	5	5	100.00
V1	csr_aliasing	adc_ctrl_csr_aliasing	5.980s	855.860us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	adc_ctrl_csr_mem_rw_with_rand_reset	3.700s	501.082us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	adc_ctrl_csr_rw	3.500s	468.632us	20	20	100.00
		adc_ctrl_csr_aliasing	5.980s	855.860us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	filters_polled	adc_ctrl_filters_polled	19.615m	503.560ms	50	50	100.00
V2	filters_polled_fixed	adc_ctrl_filters_polled_fixed	20.507m	496.899ms	50	50	100.00
V2	filters_interrupt	adc_ctrl_filters_interrupt	20.165m	494.531ms	50	50	100.00
V2	filters_interrupt_fixed	adc_ctrl_filters_interrupt_fixed	22.838m	494.750ms	50	50	100.00
V2	filters_wakeup	adc_ctrl_filters_wakeup	22.270m	574.848ms	50	50	100.00
V2	filters_wakeup_fixed	adc_ctrl_filters_wakeup_fixed	26.274m	623.454ms	50	50	100.00
V2	filters_both	adc_ctrl_filters_both	23.906m	501.667ms	49	50	98.00
V2	clock_gating	adc_ctrl_clock_gating	21.952m	515.707ms	37	50	74.00
V2	poweron_counter	adc_ctrl_poweron_counter	19.660s	5.224ms	50	50	100.00
V2	lowpower_counter	adc_ctrl_lowpower_counter	2.303m	43.689ms	50	50	100.00
V2	fsm_reset	adc_ctrl_fsm_reset	6.787m	145.572ms	50	50	100.00
V2	stress_all	adc_ctrl_stress_all	43.780m	1.257s	49	50	98.00
V2	alert_test	adc_ctrl_alert_test	3.840s	511.470us	50	50	100.00
V2	intr_test	adc_ctrl_intr_test	3.830s	506.107us	50	50	100.00
V2	tl_d_oob_addr_access	adc_ctrl_tl_errors	4.830s	473.733us	20	20	100.00
V2	tl_d_illegal_access	adc_ctrl_tl_errors	4.830s	473.733us	20	20	100.00
V2	tl_d_outstanding_access	adc_ctrl_csr_hw_reset	4.490s	1.240ms	5	5	100.00
		adc_ctrl_csr_rw	3.500s	468.632us	20	20	100.00
		adc_ctrl_csr_aliasing	5.980s	855.860us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.060s	4.671ms	20	20	100.00
V2	tl_d_partial_access	adc_ctrl_csr_hw_reset	4.490s	1.240ms	5	5	100.00
		adc_ctrl_csr_rw	3.500s	468.632us	20	20	100.00
		adc_ctrl_csr_aliasing	5.980s	855.860us	5	5	100.00
		adc_ctrl_same_csr_outstanding	15.060s	4.671ms	20	20	100.00
V2		TOTAL			725	740	97.97
V2S	tl_intg_err	adc_ctrl_sec_cm	10.030s	4.128ms	5	5	100.00
		adc_ctrl_tl_intg_err	21.540s	7.349ms	20	20	100.00
V2S	sec_cm_bus_integrity	adc_ctrl_tl_intg_err	21.540s	7.349ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	adc_ctrl_stress_all_with_rand_reset	4.350m	10.000s	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			903	920	98.15

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.11	96.45	100.00	100.00	99.01	98.06	91.08

Failure Buckets

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 8 failures:
- Test adc_ctrl_clock_gating has 6 failures.
  - 6.adc_ctrl_clock_gating.13857222013775361198515044277303323070980468262236824781911213125029902566346
    Line 180, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.adc_ctrl_clock_gating.21835245784211381006869280008003661889643732440850955116435581569403150305942
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/8.adc_ctrl_clock_gating/latest/run.log
```
  UVM_FATAL @ 2000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 2000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
- Test adc_ctrl_stress_all has 1 failures.
  - 19.adc_ctrl_stress_all.43187787515323871415120334824857670400471751686414829816097679680437529726361
    Line 160, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/19.adc_ctrl_stress_all/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 40.adc_ctrl_stress_all_with_rand_reset.25474394147067808173781404758412926579399441609593801130145099194401816612442
    Line 193, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/40.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:251) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error has 6 failures:
- Test adc_ctrl_clock_gating has 5 failures.
  - 3.adc_ctrl_clock_gating.31785803844822420613196501666921212207115721248410598015046919023232340810627
    Line 163, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/3.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 194237284064 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 194237284064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.adc_ctrl_clock_gating.77479473427339362441278496395842211440753448025825331392703423472765119938767
    Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/5.adc_ctrl_clock_gating/latest/run.log
```
  UVM_ERROR @ 2958205618 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 2958205618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
- Test adc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 34.adc_ctrl_stress_all_with_rand_reset.68047500499742810650265850005036069366467961870003965030421754547614699157128
    Line 178, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/34.adc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4778540452 ps: (cip_base_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
  UVM_INFO @ 4778540452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (adc_ctrl_scoreboard.sv:405) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: adc_ctrl_reg_block.intr_state has 3 failures:

Test adc_ctrl_clock_gating has 2 failures.

2.adc_ctrl_clock_gating.45488073563075089805198465052457466238907406381186757496638396117044014908591
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/2.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 79784366492 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 79784366492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.adc_ctrl_clock_gating.114812427749416487928468312184526296092211847318141328728626070479919385190600
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/11.adc_ctrl_clock_gating/latest/run.log

  UVM_ERROR @ 79989421901 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 79989421901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test adc_ctrl_filters_both has 1 failures.

6.adc_ctrl_filters_both.43967253268804072805938349055667535540778491784484009623989101980271082157256
Line 146, in log /nightly/runs/scratch/master/adc_ctrl-sim-vcs/6.adc_ctrl_filters_both/latest/run.log

  UVM_ERROR @ 85357670300 ps: (adc_ctrl_scoreboard.sv:405) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) reg name: adc_ctrl_reg_block.intr_state
  UVM_INFO @ 85357670300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---