AES/MASKED Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	56.856us	1	1	100.00
V1	smoke	aes_smoke	14.000s	2.003ms	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	60.584us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	100.940us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	613.326us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	602.783us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	105.116us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	100.940us	20	20	100.00
		aes_csr_aliasing	7.000s	602.783us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	2.003ms	50	50	100.00
		aes_config_error	23.000s	1.348ms	50	50	100.00
		aes_stress	2.383m	7.251ms	50	50	100.00
V2	key_length	aes_smoke	14.000s	2.003ms	50	50	100.00
		aes_config_error	23.000s	1.348ms	50	50	100.00
		aes_stress	2.383m	7.251ms	50	50	100.00
V2	back2back	aes_stress	2.383m	7.251ms	50	50	100.00
		aes_b2b	27.000s	524.825us	50	50	100.00
V2	backpressure	aes_stress	2.383m	7.251ms	50	50	100.00
V2	multi_message	aes_smoke	14.000s	2.003ms	50	50	100.00
		aes_config_error	23.000s	1.348ms	50	50	100.00
		aes_stress	2.383m	7.251ms	50	50	100.00
		aes_alert_reset	1.533m	5.789ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	99.234us	50	50	100.00
		aes_config_error	23.000s	1.348ms	50	50	100.00
		aes_alert_reset	1.533m	5.789ms	50	50	100.00
V2	trigger_clear_test	aes_clear	38.000s	3.635ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	11.000s	1.026ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.533m	5.789ms	50	50	100.00
V2	stress	aes_stress	2.383m	7.251ms	50	50	100.00
V2	sideload	aes_stress	2.383m	7.251ms	50	50	100.00
		aes_sideload	8.000s	365.384us	50	50	100.00
V2	deinitialization	aes_deinit	16.000s	1.621ms	50	50	100.00
V2	stress_all	aes_stress_all	1.300m	9.086ms	10	10	100.00
V2	alert_test	aes_alert_test	6.000s	156.432us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	94.334us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	94.334us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	60.584us	5	5	100.00
		aes_csr_rw	6.000s	100.940us	20	20	100.00
		aes_csr_aliasing	7.000s	602.783us	5	5	100.00
		aes_same_csr_outstanding	6.000s	105.772us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	60.584us	5	5	100.00
		aes_csr_rw	6.000s	100.940us	20	20	100.00
		aes_csr_aliasing	7.000s	602.783us	5	5	100.00
		aes_same_csr_outstanding	6.000s	105.772us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	36.000s	1.910ms	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_cipher_fi	47.000s	10.002ms	343	350	98.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	79.663us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	79.663us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	79.663us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	79.663us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	459.277us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	2.119ms	5	5	100.00
		aes_tl_intg_err	6.000s	153.568us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	153.568us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.533m	5.789ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	79.663us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	2.003ms	50	50	100.00
		aes_stress	2.383m	7.251ms	50	50	100.00
		aes_alert_reset	1.533m	5.789ms	50	50	100.00
		aes_core_fi	17.000s	10.217ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	79.663us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	6.000s	74.349us	50	50	100.00
		aes_stress	2.383m	7.251ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.383m	7.251ms	50	50	100.00
		aes_sideload	8.000s	365.384us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	6.000s	74.349us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	6.000s	74.349us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	6.000s	74.349us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	6.000s	74.349us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	6.000s	74.349us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.383m	7.251ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.383m	7.251ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	966.269us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_cipher_fi	47.000s	10.002ms	343	350	98.00
		aes_ctr_fi	7.000s	815.227us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	966.269us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_cipher_fi	47.000s	10.002ms	343	350	98.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.002ms	343	350	98.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	966.269us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_ctr_fi	7.000s	815.227us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_cipher_fi	47.000s	10.002ms	343	350	98.00
		aes_ctr_fi	7.000s	815.227us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.533m	5.789ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_cipher_fi	47.000s	10.002ms	343	350	98.00
		aes_ctr_fi	7.000s	815.227us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_cipher_fi	47.000s	10.002ms	343	350	98.00
		aes_ctr_fi	7.000s	815.227us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_ctr_fi	7.000s	815.227us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	966.269us	50	50	100.00
		aes_control_fi	47.000s	10.004ms	286	300	95.33
		aes_cipher_fi	47.000s	10.002ms	343	350	98.00
V2S		TOTAL			962	985	97.66
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	32.000s	2.510ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1569	1602	97.94

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.45	98.63	96.52	99.47	95.77	98.07	100.00	98.96	98.99

Failure Buckets

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 59.aes_control_fi.57651587886550139707841317833308968124161201740592928398512775155692606930612
    Line 138, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010164468 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010164468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 88.aes_control_fi.14940156587261011503944706898467539981925214281288860237590926238290400225448
    Line 147, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10026683864 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026683864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.14818945846851170674071305214463993599256875595763699444817159566033282881923
Line 260, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  84790870 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  84790870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.107366797394680097701730415202573043507085946031443652401233737919331477779541
Line 977, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6562029549 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6562029549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 19.aes_cipher_fi.66905595170410345420813208868622725044032270019557118394057325840689601186384
    Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005828016 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005828016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 25.aes_cipher_fi.58373262711311504251470827233542653329567172415188516124466567187952982346720
    Line 139, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002138682 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002138682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 5 more failures.
Job timed out after * minutes has 5 failures:
- Test aes_control_fi has 5 failures.
  - 4.aes_control_fi.781825283916866171784758068898093690282344082693843955341648277159838847922
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 16.aes_control_fi.17183990309925221942181962196998054701270871484108754282752709678756325525543
    Log /nightly/runs/scratch/master/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 3 more failures.
UVM_ERROR (cip_base_vseq.sv:925) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.30574950838813996127985807156188357109562896245570252032355080768921314913755
    Line 268, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1111907206 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1111907206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.aes_stress_all_with_rand_reset.58770722057263021188982438753998618265615407513081801666149207171600182993575
    Line 430, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 472690974 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 472690974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.3024974914474648969948636683258192571465717816150068037319781174057647301557
    Line 852, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1097038262 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1097038262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,865): Assertion AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

24.aes_core_fi.16130941870234308712839480686655144861990109621886800091528104149513964225646
Line 133, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/24.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 27529500 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 27489500 PS)
  UVM_ERROR @  27529500 ps: (aes_cipher_core.sv:865) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateKeyExpand
  UVM_INFO @  27529500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 26.aes_core_fi.60807679233288982076942625252446411805324151076160988454465572245807160502939
    Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10217211780 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10217211780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```