AES/UNMASKED Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	52.873us	1	1	100.00
V1	smoke	aes_smoke	6.000s	216.691us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	46.000s	79.311us	5	5	100.00
V1	csr_rw	aes_csr_rw	46.000s	72.486us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	50.000s	899.718us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	47.000s	179.775us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	46.000s	109.393us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	46.000s	72.486us	20	20	100.00
		aes_csr_aliasing	47.000s	179.775us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	6.000s	216.691us	50	50	100.00
		aes_config_error	6.000s	97.675us	50	50	100.00
		aes_stress	6.000s	108.493us	50	50	100.00
V2	key_length	aes_smoke	6.000s	216.691us	50	50	100.00
		aes_config_error	6.000s	97.675us	50	50	100.00
		aes_stress	6.000s	108.493us	50	50	100.00
V2	back2back	aes_stress	6.000s	108.493us	50	50	100.00
		aes_b2b	9.000s	324.516us	50	50	100.00
V2	backpressure	aes_stress	6.000s	108.493us	50	50	100.00
V2	multi_message	aes_smoke	6.000s	216.691us	50	50	100.00
		aes_config_error	6.000s	97.675us	50	50	100.00
		aes_stress	6.000s	108.493us	50	50	100.00
		aes_alert_reset	6.000s	255.379us	49	50	98.00
V2	failure_test	aes_man_cfg_err	6.000s	139.211us	50	50	100.00
		aes_config_error	6.000s	97.675us	50	50	100.00
		aes_alert_reset	6.000s	255.379us	49	50	98.00
V2	trigger_clear_test	aes_clear	7.000s	297.992us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	299.128us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	255.379us	49	50	98.00
V2	stress	aes_stress	6.000s	108.493us	50	50	100.00
V2	sideload	aes_stress	6.000s	108.493us	50	50	100.00
		aes_sideload	7.000s	233.130us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	233.388us	50	50	100.00
V2	stress_all	aes_stress_all	30.000s	1.784ms	9	10	90.00
V2	alert_test	aes_alert_test	6.000s	173.643us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	47.000s	353.340us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	47.000s	353.340us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	46.000s	79.311us	5	5	100.00
		aes_csr_rw	46.000s	72.486us	20	20	100.00
		aes_csr_aliasing	47.000s	179.775us	5	5	100.00
		aes_same_csr_outstanding	46.000s	97.719us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	46.000s	79.311us	5	5	100.00
		aes_csr_rw	46.000s	72.486us	20	20	100.00
		aes_csr_aliasing	47.000s	179.775us	5	5	100.00
		aes_same_csr_outstanding	46.000s	97.719us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	7.000s	766.657us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_cipher_fi	32.000s	10.007ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	46.000s	133.437us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	46.000s	133.437us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	46.000s	133.437us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	46.000s	133.437us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	48.000s	493.172us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.333ms	5	5	100.00
		aes_tl_intg_err	49.000s	1.438ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	49.000s	1.438ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	255.379us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	46.000s	133.437us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	6.000s	216.691us	50	50	100.00
		aes_stress	6.000s	108.493us	50	50	100.00
		aes_alert_reset	6.000s	255.379us	49	50	98.00
		aes_core_fi	2.050m	10.022ms	63	70	90.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	46.000s	133.437us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	57.251us	50	50	100.00
		aes_stress	6.000s	108.493us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	108.493us	50	50	100.00
		aes_sideload	7.000s	233.130us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	57.251us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	57.251us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	57.251us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	57.251us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	57.251us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	108.493us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	108.493us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	98.662us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_cipher_fi	32.000s	10.007ms	329	350	94.00
		aes_ctr_fi	5.000s	332.246us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	98.662us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_cipher_fi	32.000s	10.007ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	32.000s	10.007ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	98.662us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_ctr_fi	5.000s	332.246us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_cipher_fi	32.000s	10.007ms	329	350	94.00
		aes_ctr_fi	5.000s	332.246us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	255.379us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_cipher_fi	32.000s	10.007ms	329	350	94.00
		aes_ctr_fi	5.000s	332.246us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_cipher_fi	32.000s	10.007ms	329	350	94.00
		aes_ctr_fi	5.000s	332.246us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_ctr_fi	5.000s	332.246us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	98.662us	50	50	100.00
		aes_control_fi	35.000s	10.004ms	279	300	93.00
		aes_cipher_fi	32.000s	10.007ms	329	350	94.00
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	18.000s	2.138ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1541	1602	96.19

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.41	97.75	94.93	98.84	93.69	98.07	93.33	98.65	98.79

Failure Buckets

Job timed out after * minutes has 22 failures:
- Test aes_control_fi has 10 failures.
  - 5.aes_control_fi.82672464905807606160404460907357077746810846585881775296059241157489620131433
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 25.aes_control_fi.64335132008359759862958529290999747952492197409464455278232978469597224759251
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
- Test aes_cipher_fi has 12 failures.
  - 26.aes_cipher_fi.78877487290984692277730387953215145539854871346819581521938816961807129117766
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/26.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 32.aes_cipher_fi.64443337681422582249897429754560034129705755411667906664686873713345431962435
    Log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 20.aes_control_fi.111639654048329900516465953979139626610168303069694768125312447593801978408084
    Line 134, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010029764 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010029764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 41.aes_control_fi.58676573418249829714115014006358335899295630428842750064184989530473377675645
    Line 136, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/41.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10031321251 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10031321251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 36.aes_cipher_fi.98256107392494255614754837133015887018813873621199137174937093903497443847909
    Line 139, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009432390 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009432390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 39.aes_cipher_fi.109169347711071279314007597689033592770766587537226207488724881704431399764800
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003859992 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003859992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.48417971123784458889211360856309923424731708945312664722459813967571480790190
Line 215, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2138230053 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2138230053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.74433080257607526891291091168300552163940980099326613649803834772055423861755
Line 209, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 950619948 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 950619948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 36.aes_core_fi.18805580956693973480208198137080809096170240154292317418351520069218649697930
    Line 133, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10058179397 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10058179397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 49.aes_core_fi.49545108705465481972896832632451478848066663456897505293227779000569512024613
    Line 130, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10036855676 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10036855676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 39.aes_core_fi.64306069349458265188609303881303350364477174272575732645425292609897201696928
    Line 141, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/39.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006246102 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006246102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 62.aes_core_fi.114891867473274900768962152880525742968353316469095031858035173877650816204264
    Line 147, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10023356300 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023356300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.40761672510514750143161556102279255792228956590084447494457541149835377045005
    Line 204, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  27293137 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  27293137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.aes_stress_all_with_rand_reset.113132747073506183587374359217808999554072256021369231211670723134534282919746
    Line 465, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1162790800 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1162790800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

5.aes_stress_all.105166505535518969862163734467980154879974758088889911532536120405365782841790
Line 96981, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/5.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 364503954 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 364493954 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 364503954 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 364493954 PS)
  UVM_ERROR @ 364503954 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.110207430190849899558277548243746452602243751750525086535496082740173385087188
    Line 157, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  18881474 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  18881474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

33.aes_alert_reset.1096304302471876003955625787571599392418784082468829679343457348669593683097
Line 329, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/33.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 16269074 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 16248666 PS)
  UVM_ERROR @  16269074 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  16269074 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 42.aes_core_fi.2831452983752843975414743040132924246858401334366908822684932698811264071703
    Line 140, in log /nightly/runs/scratch/master/aes_unmasked-sim-xcelium/42.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021602731 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xff2a2b84, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10021602731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```