CSRNG Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	9.000s	272.230us	50	50	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	5.000s	33.885us	5	5	100.00
V1	csr_rw	csrng_csr_rw	6.000s	69.944us	20	20	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	18.000s	351.508us	5	5	100.00
V1	csr_aliasing	csrng_csr_aliasing	10.000s	411.537us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	7.000s	275.684us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	6.000s	69.944us	20	20	100.00
		csrng_csr_aliasing	10.000s	411.537us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	interrupts	csrng_intr	27.000s	1.852ms	198	200	99.00
V2	alerts	csrng_alert	1.200m	4.043ms	500	500	100.00
V2	err	csrng_err	10.000s	26.437us	498	500	99.60
V2	cmds	csrng_cmds	6.100m	24.098ms	50	50	100.00
V2	life cycle	csrng_cmds	6.100m	24.098ms	50	50	100.00
V2	stress_all	csrng_stress_all	30.283m	98.088ms	49	50	98.00
V2	intr_test	csrng_intr_test	7.000s	158.125us	50	50	100.00
V2	alert_test	csrng_alert_test	7.000s	175.470us	50	50	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	12.000s	554.871us	20	20	100.00
V2	tl_d_illegal_access	csrng_tl_errors	12.000s	554.871us	20	20	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	5.000s	33.885us	5	5	100.00
		csrng_csr_rw	6.000s	69.944us	20	20	100.00
		csrng_csr_aliasing	10.000s	411.537us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	370.335us	20	20	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	5.000s	33.885us	5	5	100.00
		csrng_csr_rw	6.000s	69.944us	20	20	100.00
		csrng_csr_aliasing	10.000s	411.537us	5	5	100.00
		csrng_same_csr_outstanding	10.000s	370.335us	20	20	100.00
V2		TOTAL			1435	1440	99.65
V2S	tl_intg_err	csrng_sec_cm	7.000s	43.887us	5	5	100.00
		csrng_tl_intg_err	17.000s	1.336ms	20	20	100.00
V2S	sec_cm_config_regwen	csrng_regwen	7.000s	45.890us	50	50	100.00
		csrng_csr_rw	6.000s	69.944us	20	20	100.00
V2S	sec_cm_config_mubi	csrng_alert	1.200m	4.043ms	500	500	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	30.283m	98.088ms	49	50	98.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	1.200m	4.043ms	500	500	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
V2S	sec_cm_constants_lc_gated	csrng_stress_all	30.283m	98.088ms	49	50	98.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	1.200m	4.043ms	500	500	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	17.000s	1.336ms	20	20	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
		csrng_sec_cm	7.000s	43.887us	5	5	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	27.000s	1.852ms	198	200	99.00
		csrng_err	10.000s	26.437us	498	500	99.60
V2S		TOTAL			75	75	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	1.583m	6.699ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1615	1630	99.08

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.74	98.61	96.63	99.94	97.30	92.08	100.00	97.36	90.72

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:925) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 10 failures:
- Test csrng_stress_all_with_rand_reset has 10 failures.
  - 0.csrng_stress_all_with_rand_reset.109276815562564861516931570408741391066495741564066769074127519837608814388310
    Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 441168547 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 441168547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.csrng_stress_all_with_rand_reset.58393172571752430984752491066677812307486590536680135934569489253151551149235
    Line 99, in log /nightly/runs/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 719416692 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 719416692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.

xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_*/rtl/csrng_cmd_stage.sv,518): Assertion CsrngCmdStageGenbitsFifoPushExpected_A has failed has 2 failures:

Test csrng_intr has 2 failures.

7.csrng_intr.35195525922400488712855373146886127001214167269367897651338290946041409259334
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/7.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 77112065 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @  77112065 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @  77112065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

97.csrng_intr.87482610398799110831989092560808013578833459947226985560172647937941807210851
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/97.csrng_intr/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/csrng-sim-xcelium/default/src/lowrisc_ip_csrng_0.1/rtl/csrng_cmd_stage.sv,518): (time 231487052 PS) Assertion tb.dut.u_csrng_core.gen_cmd_stage[2].u_csrng_cmd_stage.CsrngCmdStageGenbitsFifoPushExpected_A has failed
  UVM_ERROR @ 231487052 ps: (csrng_cmd_stage.sv:518) [ASSERT FAILED] CsrngCmdStageGenbitsFifoPushExpected_A
  UVM_INFO @ 231487052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: * has 2 failures:

Test csrng_err has 2 failures.

167.csrng_err.52963557874802126994022967000067895415504473545470908570435809880255417966193
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/167.csrng_err/latest/run.log

  UVM_ERROR @  11449602 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  11449602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

486.csrng_err.38871764203604727830389469099288680650650130148840506649273403030175364785730
Line 133, in log /nightly/runs/scratch/master/csrng-sim-xcelium/486.csrng_err/latest/run.log

  UVM_ERROR @  13173229 ps: (csr_utils_pkg.sv:468) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: csrng_reg_block.err_code.cmd_gen_cnt_err reset value: 0x0
  UVM_INFO @  13173229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:
- Test csrng_stress_all has 1 failures.
  - 28.csrng_stress_all.37934116444575157939069292032043358774097560482871845015795962665884367520928
    Line 151, in log /nightly/runs/scratch/master/csrng-sim-xcelium/28.csrng_stress_all/latest/run.log
```
  UVM_ERROR @ 11527403384 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
  UVM_INFO @ 11527403384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```