EDN Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 2.820s 18.643us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 2.380s 17.401us 5 5 100.00
V1 csr_rw edn_csr_rw 2.560s 12.431us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.090s 212.881us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.640s 111.696us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.950s 122.429us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 2.560s 12.431us 20 20 100.00
edn_csr_aliasing 2.640s 111.696us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.384m 4.479ms 300 300 100.00
V2 csrng_commands edn_genbits 1.384m 4.479ms 300 300 100.00
V2 genbits edn_genbits 1.384m 4.479ms 300 300 100.00
V2 interrupts edn_intr 2.980s 20.967us 50 50 100.00
V2 alerts edn_alert 3.050s 27.834us 200 200 100.00
V2 errs edn_err 3.050s 33.896us 100 100 100.00
V2 disable edn_disable 2.810s 32.490us 50 50 100.00
edn_disable_auto_req_mode 3.050s 71.650us 50 50 100.00
V2 stress_all edn_stress_all 7.630s 559.352us 50 50 100.00
V2 intr_test edn_intr_test 2.570s 15.532us 50 50 100.00
V2 alert_test edn_alert_test 3.150s 52.581us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.470s 420.901us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.470s 420.901us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 2.380s 17.401us 5 5 100.00
edn_csr_rw 2.560s 12.431us 20 20 100.00
edn_csr_aliasing 2.640s 111.696us 5 5 100.00
edn_same_csr_outstanding 3.080s 57.320us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 2.380s 17.401us 5 5 100.00
edn_csr_rw 2.560s 12.431us 20 20 100.00
edn_csr_aliasing 2.640s 111.696us 5 5 100.00
edn_same_csr_outstanding 3.080s 57.320us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.710s 947.119us 5 5 100.00
edn_tl_intg_err 7.870s 489.748us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 2.690s 19.468us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 3.050s 27.834us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.710s 947.119us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.710s 947.119us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.710s 947.119us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.710s 947.119us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 3.050s 27.834us 200 200 100.00
edn_sec_cm 9.710s 947.119us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 3.050s 27.834us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 7.870s 489.748us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.617m 16.151ms 30 50 60.00
V3 TOTAL 30 50 60.00
TOTAL 1110 1130 98.23

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.64 98.32 94.29 97.07 90.70 96.36 99.78 92.94

Failure Buckets