ENTROPY_SRC Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 6.000s 42.126us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 172.399us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 65.165us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 10.000s 259.200us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 6.000s 45.248us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 5.000s 211.400us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 65.165us 20 20 100.00
entropy_src_csr_aliasing 6.000s 45.248us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 6.000s 42.126us 50 50 100.00
entropy_src_rng 4.633m 19.046ms 21 300 7.00
entropy_src_fw_ov 8.167m 20.022ms 188 300 62.67
V2 firmware_mode entropy_src_fw_ov 8.167m 20.022ms 188 300 62.67
V2 rng_mode entropy_src_rng 4.633m 19.046ms 21 300 7.00
V2 rng_max_rate entropy_src_rng_max_rate 7.883m 10.192ms 2 400 0.50
V2 health_checks entropy_src_rng 4.633m 19.046ms 21 300 7.00
V2 conditioning entropy_src_rng 4.633m 19.046ms 21 300 7.00
V2 interrupts entropy_src_rng 4.633m 19.046ms 21 300 7.00
entropy_src_intr 21.000s 557.315us 50 50 100.00
V2 alerts entropy_src_rng 4.633m 19.046ms 21 300 7.00
entropy_src_functional_alerts 8.000s 66.255us 50 50 100.00
V2 stress_all entropy_src_stress_all 7.833m 18.047ms 45 50 90.00
V2 functional_errors entropy_src_functional_errors 6.233m 10.013ms 970 1000 97.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 25.000s 337.436us 49 50 98.00
V2 intr_test entropy_src_intr_test 5.000s 20.437us 50 50 100.00
V2 alert_test entropy_src_alert_test 6.000s 258.361us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 128.892us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 128.892us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 172.399us 5 5 100.00
entropy_src_csr_rw 5.000s 65.165us 20 20 100.00
entropy_src_csr_aliasing 6.000s 45.248us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 142.312us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 172.399us 5 5 100.00
entropy_src_csr_rw 5.000s 65.165us 20 20 100.00
entropy_src_csr_aliasing 6.000s 45.248us 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 142.312us 20 20 100.00
V2 TOTAL 1515 2340 64.74
V2S tl_intg_err entropy_src_sec_cm 6.000s 169.318us 5 5 100.00
entropy_src_tl_intg_err 8.000s 194.314us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.633m 19.046ms 21 300 7.00
entropy_src_cfg_regwen 6.000s 202.209us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.633m 19.046ms 21 300 7.00
V2S sec_cm_config_redun entropy_src_rng 4.633m 19.046ms 21 300 7.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.633m 19.046ms 21 300 7.00
entropy_src_fw_ov 8.167m 20.022ms 188 300 62.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 6.233m 10.013ms 970 1000 97.00
entropy_src_sec_cm 6.000s 169.318us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 6.233m 10.013ms 970 1000 97.00
entropy_src_sec_cm 6.000s 169.318us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.633m 19.046ms 21 300 7.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 6.233m 10.013ms 970 1000 97.00
entropy_src_sec_cm 6.000s 169.318us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 6.233m 10.013ms 970 1000 97.00
entropy_src_sec_cm 6.000s 169.318us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 6.233m 10.013ms 970 1000 97.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 8.000s 66.255us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 8.000s 194.314us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 5.183m 13.081ms 4 50 8.00
V3 TOTAL 4 50 8.00
TOTAL 1699 2570 66.11

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
96.18 98.15 95.33 98.33 95.46 96.59 96.88 90.68 87.45

Failure Buckets