HMAC Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	hmac_smoke	13.120s	2.431ms	10	10	100.00
V1	csr_hw_reset	hmac_csr_hw_reset	2.460s	105.069us	5	5	100.00
V1	csr_rw	hmac_csr_rw	2.560s	59.998us	20	20	100.00
V1	csr_bit_bash	hmac_csr_bit_bash	14.600s	2.200ms	5	5	100.00
V1	csr_aliasing	hmac_csr_aliasing	6.870s	531.203us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	hmac_csr_mem_rw_with_rand_reset	13.880m	102.479ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	hmac_csr_rw	2.560s	59.998us	20	20	100.00
		hmac_csr_aliasing	6.870s	531.203us	5	5	100.00
V1		TOTAL			65	65	100.00
V2	long_msg	hmac_long_msg	49.440s	6.768ms	10	10	100.00
V2	back_pressure	hmac_back_pressure	1.547m	4.327ms	25	25	100.00
V2	test_vectors	hmac_test_sha256_vectors	4.161m	6.431ms	30	30	100.00
		hmac_test_sha384_vectors	9.401m	15.540ms	75	75	100.00
		hmac_test_sha512_vectors	9.614m	84.684ms	75	75	100.00
		hmac_test_hmac256_vectors	16.050s	366.306us	50	50	100.00
		hmac_test_hmac384_vectors	17.320s	1.618ms	60	60	100.00
		hmac_test_hmac512_vectors	20.220s	382.889us	75	75	100.00
V2	burst_wr	hmac_burst_wr	35.300s	3.984ms	50	50	100.00
V2	datapath_stress	hmac_datapath_stress	18.286m	12.448ms	10	10	100.00
V2	error	hmac_error	1.478m	8.110ms	10	10	100.00
V2	wipe_secret	hmac_wipe_secret	1.647m	5.002ms	10	10	100.00
V2	save_and_restore	hmac_smoke	13.120s	2.431ms	10	10	100.00
		hmac_long_msg	49.440s	6.768ms	10	10	100.00
		hmac_back_pressure	1.547m	4.327ms	25	25	100.00
		hmac_datapath_stress	18.286m	12.448ms	10	10	100.00
		hmac_burst_wr	35.300s	3.984ms	50	50	100.00
		hmac_stress_all	40.554m	103.710ms	50	50	100.00
V2	fifo_empty_status_interrupt	hmac_smoke	13.120s	2.431ms	10	10	100.00
		hmac_long_msg	49.440s	6.768ms	10	10	100.00
		hmac_back_pressure	1.547m	4.327ms	25	25	100.00
		hmac_datapath_stress	18.286m	12.448ms	10	10	100.00
		hmac_wipe_secret	1.647m	5.002ms	10	10	100.00
		hmac_test_sha256_vectors	4.161m	6.431ms	30	30	100.00
		hmac_test_sha384_vectors	9.401m	15.540ms	75	75	100.00
		hmac_test_sha512_vectors	9.614m	84.684ms	75	75	100.00
		hmac_test_hmac256_vectors	16.050s	366.306us	50	50	100.00
		hmac_test_hmac384_vectors	17.320s	1.618ms	60	60	100.00
		hmac_test_hmac512_vectors	20.220s	382.889us	75	75	100.00
V2	wide_digest_configurable_key_length	hmac_smoke	13.120s	2.431ms	10	10	100.00
		hmac_long_msg	49.440s	6.768ms	10	10	100.00
		hmac_back_pressure	1.547m	4.327ms	25	25	100.00
		hmac_datapath_stress	18.286m	12.448ms	10	10	100.00
		hmac_burst_wr	35.300s	3.984ms	50	50	100.00
		hmac_error	1.478m	8.110ms	10	10	100.00
		hmac_wipe_secret	1.647m	5.002ms	10	10	100.00
		hmac_test_sha256_vectors	4.161m	6.431ms	30	30	100.00
		hmac_test_sha384_vectors	9.401m	15.540ms	75	75	100.00
		hmac_test_sha512_vectors	9.614m	84.684ms	75	75	100.00
		hmac_test_hmac256_vectors	16.050s	366.306us	50	50	100.00
		hmac_test_hmac384_vectors	17.320s	1.618ms	60	60	100.00
		hmac_test_hmac512_vectors	20.220s	382.889us	75	75	100.00
		hmac_stress_all	40.554m	103.710ms	50	50	100.00
V2	stress_all	hmac_stress_all	40.554m	103.710ms	50	50	100.00
V2	alert_test	hmac_alert_test	2.950s	15.936us	50	50	100.00
V2	intr_test	hmac_intr_test	2.160s	48.337us	50	50	100.00
V2	tl_d_oob_addr_access	hmac_tl_errors	5.130s	2.039ms	20	20	100.00
V2	tl_d_illegal_access	hmac_tl_errors	5.130s	2.039ms	20	20	100.00
V2	tl_d_outstanding_access	hmac_csr_hw_reset	2.460s	105.069us	5	5	100.00
		hmac_csr_rw	2.560s	59.998us	20	20	100.00
		hmac_csr_aliasing	6.870s	531.203us	5	5	100.00
		hmac_same_csr_outstanding	3.730s	529.391us	20	20	100.00
V2	tl_d_partial_access	hmac_csr_hw_reset	2.460s	105.069us	5	5	100.00
		hmac_csr_rw	2.560s	59.998us	20	20	100.00
		hmac_csr_aliasing	6.870s	531.203us	5	5	100.00
		hmac_same_csr_outstanding	3.730s	529.391us	20	20	100.00
V2		TOTAL			670	670	100.00
V2S	tl_intg_err	hmac_sec_cm	3.260s	136.386us	5	5	100.00
		hmac_tl_intg_err	6.150s	1.164ms	20	20	100.00
V2S	sec_cm_bus_integrity	hmac_tl_intg_err	6.150s	1.164ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	write_config_and_secret_key_during_msg_wr	hmac_smoke	13.120s	2.431ms	10	10	100.00
V3	stress_reset	hmac_stress_reset	9.600s	201.281us	25	25	100.00
V3	stress_all_with_rand_reset	hmac_stress_all_with_rand_reset	6.030m	11.964ms	35	35	100.00
V3		TOTAL			60	60	100.00
	Unmapped tests	hmac_directed	1.910s	45.372us	1	1	100.00
		TOTAL			821	821	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
92.06	100.00	97.14	100.00	100.00	100.00	100.00	47.30