I2C Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	1.429m	2.077ms	50	50	100.00
V1	target_smoke	i2c_target_smoke	38.450s	5.112ms	50	50	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	2.330s	60.745us	5	5	100.00
V1	csr_rw	i2c_csr_rw	2.210s	46.256us	20	20	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.830s	362.729us	5	5	100.00
V1	csr_aliasing	i2c_csr_aliasing	3.260s	198.296us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.780s	36.959us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	2.210s	46.256us	20	20	100.00
		i2c_csr_aliasing	3.260s	198.296us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	host_error_intr	i2c_host_error_intr	14.360s	312.769us	49	50	98.00
V2	host_stress_all	i2c_host_stress_all	43.747m	88.468ms	21	50	42.00
V2	host_maxperf	i2c_host_perf	49.685m	72.909ms	50	50	100.00
V2	host_override	i2c_host_override	2.500s	47.616us	50	50	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	5.236m	5.344ms	50	50	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	2.621m	12.772ms	50	50	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.950s	337.579us	50	50	100.00
		i2c_host_fifo_fmt_empty	20.790s	1.917ms	50	50	100.00
		i2c_host_fifo_reset_rx	12.420s	446.027us	50	50	100.00
V2	host_fifo_full	i2c_host_fifo_full	3.551m	6.251ms	50	50	100.00
V2	host_timeout	i2c_host_stretch_timeout	37.350s	3.911ms	50	50	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	5.690s	382.582us	15	50	30.00
V2	target_glitch	i2c_target_glitch	14.870s	11.583ms	2	2	100.00
V2	target_stress_all	i2c_target_stress_all	16.227m	52.825ms	48	50	96.00
V2	target_maxperf	i2c_target_perf	10.620s	2.015ms	50	50	100.00
V2	target_fifo_empty	i2c_target_stress_rd	1.434m	7.331ms	50	50	100.00
		i2c_target_intr_smoke	12.360s	16.485ms	50	50	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	3.570s	256.503us	50	50	100.00
		i2c_target_fifo_reset_tx	3.610s	295.870us	50	50	100.00
V2	target_fifo_full	i2c_target_stress_wr	19.590m	64.643ms	50	50	100.00
		i2c_target_stress_rd	1.434m	7.331ms	50	50	100.00
		i2c_target_intr_stress_wr	5.762m	23.493ms	50	50	100.00
V2	target_timeout	i2c_target_timeout	11.120s	6.338ms	50	50	100.00
V2	target_clock_stretch	i2c_target_stretch	2.734m	4.922ms	44	50	88.00
V2	bad_address	i2c_target_bad_addr	9.880s	6.206ms	50	50	100.00
V2	target_mode_glitch	i2c_target_hrst	43.370s	10.117ms	22	50	44.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	5.310s	2.328ms	50	50	100.00
		i2c_target_fifo_watermarks_tx	3.420s	445.432us	50	50	100.00
V2	host_mode_config_perf	i2c_host_perf	49.685m	72.909ms	50	50	100.00
		i2c_host_perf_precise	17.558m	24.301ms	50	50	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	37.350s	3.911ms	50	50	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	16.490s	1.297ms	46	50	92.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	5.230s	1.241ms	50	50	100.00
		i2c_target_nack_acqfull_addr	5.250s	7.206ms	50	50	100.00
		i2c_target_nack_txstretch	3.410s	841.025us	39	50	78.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	28.480s	2.843ms	50	50	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	4.960s	506.267us	50	50	100.00
V2	alert_test	i2c_alert_test	2.200s	102.561us	50	50	100.00
V2	intr_test	i2c_intr_test	2.320s	21.074us	50	50	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	3.250s	426.750us	20	20	100.00
V2	tl_d_illegal_access	i2c_tl_errors	3.250s	426.750us	20	20	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	2.330s	60.745us	5	5	100.00
		i2c_csr_rw	2.210s	46.256us	20	20	100.00
		i2c_csr_aliasing	3.260s	198.296us	5	5	100.00
		i2c_same_csr_outstanding	2.430s	60.397us	19	20	95.00
V2	tl_d_partial_access	i2c_csr_hw_reset	2.330s	60.745us	5	5	100.00
		i2c_csr_rw	2.210s	46.256us	20	20	100.00
		i2c_csr_aliasing	3.260s	198.296us	5	5	100.00
		i2c_same_csr_outstanding	2.430s	60.397us	19	20	95.00
V2		TOTAL			1675	1792	93.47
V2S	tl_intg_err	i2c_tl_intg_err	3.920s	2.779ms	20	20	100.00
		i2c_sec_cm	2.550s	139.891us	5	5	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	3.920s	2.779ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	44.470s	1.021ms	0	10	0.00
V3	target_error_intr	i2c_target_unexp_stop	4.750s	2.251ms	0	50	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	19.110s	2.409ms	0	10	0.00
V3		TOTAL			0	70	0.00
		TOTAL			1855	2042	90.84

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.05	97.38	89.78	74.17	72.02	94.34	98.52	90.17

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 41 failures:

Test i2c_host_stress_all has 24 failures.

1.i2c_host_stress_all.71802183981393106043385727631851554193789333818041263462507603981381794015736
Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 57312178085 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3872780

3.i2c_host_stress_all.58977501727788622249254945597020568944922593123656695061415652025708093293218
Line 189, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 40266312209 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @3316748

... and 22 more failures.

Test i2c_host_mode_toggle has 17 failures.

5.i2c_host_mode_toggle.51060502502148051516530149739360887975019369716725192724118324200377168940305
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/5.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 662520838 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @53203

6.i2c_host_mode_toggle.41163800781513342768563452646964425096386174051696053645992383548385725698323
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  89604998 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @13467

... and 15 more failures.

UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 35 failures:
- Test i2c_target_unexp_stop has 33 failures.
  - 0.i2c_target_unexp_stop.22641476676000753129414306346763860977108628557608806709571899443679997795239
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 385300227 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 3 [0x3])
  UVM_INFO @ 385300227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.i2c_target_unexp_stop.62008731722163585515796143834823883026108545555965205131292094733022005950216
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 107345225 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 5 [0x5])
  UVM_INFO @ 107345225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 31 more failures.
- Test i2c_target_stress_all_with_rand_reset has 2 failures.
  - 3.i2c_target_stress_all_with_rand_reset.12361905454612563827675709474624909830076410120896189364855301861827682538151
    Line 104, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 907168333 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 130 [0x82])
  UVM_INFO @ 907168333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 6.i2c_target_stress_all_with_rand_reset.46294734104533545271909580524592937011767957372171595407072148850686508816171
    Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/6.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  43362003 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 27 [0x1b])
  UVM_INFO @  43362003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 28 failures:
- Test i2c_target_hrst has 28 failures.
  - 0.i2c_target_hrst.61256286716169112446898182201625925754111399824900998272907918602781971581100
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10003657455 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10003657455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.i2c_target_hrst.48452606526574519212660350231348697805094754087136811664603852760707011881943
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10497593417 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10497593417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 26 more failures.

UVM_ERROR (cip_base_vseq.sv:924) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 16 failures:

Test i2c_host_stress_all_with_rand_reset has 10 failures.

0.i2c_host_stress_all_with_rand_reset.105508416837241296390711180472810641461192204388706465055972075972270418956656
Line 87, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2553661439 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2553661439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_host_stress_all_with_rand_reset.28874857279651826710831296959066382734743415492141825803859400496053183584041
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4362254849 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 4362254849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test i2c_target_stress_all_with_rand_reset has 6 failures.

0.i2c_target_stress_all_with_rand_reset.25477110003259158546266130745405754068887609514972266144939113917854619232018
Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 325494586 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 325494586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.i2c_target_stress_all_with_rand_reset.48552987515910672270551795769097757039642933752008406124516959643576610714530
Line 107, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_target_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3991004358 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3991004358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 14 failures:

Test i2c_host_mode_toggle has 14 failures.

0.i2c_host_mode_toggle.90221636246791165007713158889236941047970964906529275474808537863026121822674
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  60154608 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

1.i2c_host_mode_toggle.62634686978886493290453047063531627844090268380638847800885442736404711983505
Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/1.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 188157384 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
  --> EXP:
  ---------------------------------------------------
  Name            Type                Size  Value
  ---------------------------------------------------

... and 12 more failures.

UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 14 failures:
- Test i2c_target_unexp_stop has 14 failures.
  - 2.i2c_target_unexp_stop.105529086013411209402447157600741548625504609135271373411204680770735108039313
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 149762705 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 149762705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.i2c_target_unexp_stop.93083292366345915182191849458280309043431953217349052150220275065926234297227
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  85496014 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
  UVM_INFO @  85496014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 11 failures:
- Test i2c_target_nack_txstretch has 11 failures.
  - 2.i2c_target_nack_txstretch.64786165060942249100579207927483091694624545871159000842429602078109804691679
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 174613865 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 174613865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 15.i2c_target_nack_txstretch.100164088422356509770175034768435522524498704617551688935635824724420810301200
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/15.i2c_target_nack_txstretch/latest/run.log
```
  UVM_ERROR @ 162315642 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
  UVM_INFO @ 162315642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 9 more failures.
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred! has 6 failures:
- Test i2c_target_stretch has 6 failures.
  - 7.i2c_target_stretch.51659257156614188831038570858246418753491614717516289309500410192914962212457
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10001740470 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10001740470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 11.i2c_target_stretch.14538434625324714796527804687080133279271692397004444360929984491283961122648
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/11.i2c_target_stretch/latest/run.log
```
  UVM_FATAL @ 10180240581 ps: (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!
  UVM_INFO @ 10180240581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
- Test i2c_host_mode_toggle has 4 failures.
  - 2.i2c_host_mode_toggle.63575228660626839450613187065107134689334141909594793182046911079609079870411
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/2.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @ 266456997 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0xbd4a7114, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @ 266456997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 24.i2c_host_mode_toggle.13775214629165523391992773623301301815256699712623433983139470330469265682257
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/24.i2c_host_mode_toggle/latest/run.log
```
  UVM_FATAL @  39465570 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout i2c_reg_block.status.hostidle (addr=0x4ad7a694, Comparison=CompareOpEq, exp_data=0x1, call_count=3)
  UVM_INFO @  39465570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 2 more failures.
Job timed out after * minutes has 4 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 4.i2c_target_stress_all_with_rand_reset.98314028905765631666939649117875508587467253573537819013389067538141799566678
    Log /nightly/runs/scratch/master/i2c-sim-vcs/4.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 20 minutes
```
- Test i2c_host_error_intr has 1 failures.
  - 10.i2c_host_error_intr.83811092348901065955402419152328252883507888735708420688239760734825501772799
    Log /nightly/runs/scratch/master/i2c-sim-vcs/10.i2c_host_error_intr/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_target_stress_all has 1 failures.
  - 16.i2c_target_stress_all.110148700937846085019302237556595691304850643245945880876118643474108222013117
    Log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_target_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
- Test i2c_host_stress_all has 1 failures.
  - 33.i2c_host_stress_all.66601007008093946300255718089251039438566284907717510860726678227755632291622
    Log /nightly/runs/scratch/master/i2c-sim-vcs/33.i2c_host_stress_all/latest/run.log
```
  Job timed out after 60 minutes
```
Error-[CNST-CIF] Constraints inconsistency failure has 4 failures:
- Test i2c_target_tx_stretch_ctrl has 4 failures.
  - 7.i2c_target_tx_stretch_ctrl.58162147168857005091197303371554053718100200612194118177364255769687270520625
    Line 118, in log /nightly/runs/scratch/master/i2c-sim-vcs/7.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - 8.i2c_target_tx_stretch_ctrl.85432395210931794823090357033053673286414808367701643902463693987026356945718
    Line 124, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_tx_stretch_ctrl/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_i2c_env_0.1/seq_lib/i2c_base_vseq.sv, 872
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
  - ... and 2 more failures.

UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 3 failures:

Test i2c_host_stress_all has 3 failures.

12.i2c_host_stress_all.7924096059677890229385659842415547122167334801139606830130434884495503720960
Line 138, in log /nightly/runs/scratch/master/i2c-sim-vcs/12.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 22592782153 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @767058

16.i2c_host_stress_all.15821166460413850856288233501776614713009834302289435110092965759368924903637
Line 117, in log /nightly/runs/scratch/master/i2c-sim-vcs/16.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 86815856887 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1101944

... and 1 more failures.

Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))' has 3 failures:

Test i2c_target_unexp_stop has 3 failures.

13.i2c_target_unexp_stop.28961752318221202588637537292723284627954608499768996833229477313097741223570
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/13.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @  79420684 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @  79420684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.i2c_target_unexp_stop.38303628832092992163423434803205786310226779141044020644566935782922545455754
Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/20.i2c_target_unexp_stop/latest/run.log

      Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
  UVM_ERROR @ 2757831207 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
  UVM_INFO @ 2757831207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:525) [i2c_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*]) has 1 failures:
- Test i2c_same_csr_outstanding has 1 failures.
  - 3.i2c_same_csr_outstanding.67185668372026553272618031994120899484135732383034602051960519239571252638454
    Line 72, in log /nightly/runs/scratch/master/i2c-sim-vcs/3.i2c_same_csr_outstanding/latest/run.log
```
  UVM_ERROR @ 182309704 ps: (cip_base_vseq.sv:525) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed data & ~ro_mask == 0 (64 [0x40] vs 0 [0x0])
  UVM_INFO @ 182309704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 8.i2c_target_stress_all_with_rand_reset.92464947676291695837350598565705471354467039559831254622275276808667549921657
    Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/8.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2409043016 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2409043016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred! has 1 failures:
- Test i2c_target_stress_all has 1 failures.
  - 19.i2c_target_stress_all.47357885139143355374938978607183941761969763684715235928103921143123572195736
    Line 100, in log /nightly/runs/scratch/master/i2c-sim-vcs/19.i2c_target_stress_all/latest/run.log
```
  UVM_FATAL @ 65477863190 ps: (i2c_base_vseq.sv:1343) [Failed check for ALL_ACQFIFO_READS_OCCURRED] wait timeout occurred!
  UVM_INFO @ 65477863190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test i2c_host_stress_all has 1 failures.
  - 21.i2c_host_stress_all.114965716577346488537134622839521982993214884444717287843049917796340904899576
    Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/21.i2c_host_stress_all/latest/run.log
```
  UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```