KEYMGR Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	33.240s	5.101ms	49	50	98.00
V1	random	keymgr_random	49.620s	2.911ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	2.610s	26.204us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	2.720s	21.558us	14	20	70.00
V1	csr_bit_bash	keymgr_csr_bit_bash	12.600s	1.764ms	3	5	60.00
V1	csr_aliasing	keymgr_csr_aliasing	6.870s	855.595us	4	5	80.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	3.240s	49.042us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.720s	21.558us	14	20	70.00
		keymgr_csr_aliasing	6.870s	855.595us	4	5	80.00
V1		TOTAL			143	155	92.26
V2	cfgen_during_op	keymgr_cfg_regwen	1.526m	2.626ms	48	50	96.00
V2	sideload	keymgr_sideload	1.004m	7.042ms	50	50	100.00
		keymgr_sideload_kmac	30.190s	4.615ms	49	50	98.00
		keymgr_sideload_aes	43.480s	1.953ms	50	50	100.00
		keymgr_sideload_otbn	27.140s	795.862us	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	27.260s	1.729ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.410s	275.138us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	17.260s	2.883ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.300m	8.781ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	39.830s	2.201ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	16.640s	2.008ms	50	50	100.00
V2	stress_all	keymgr_stress_all	5.149m	58.387ms	48	50	96.00
V2	intr_test	keymgr_intr_test	2.340s	26.836us	50	50	100.00
V2	alert_test	keymgr_alert_test	2.490s	70.582us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.130s	129.381us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.130s	129.381us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	2.610s	26.204us	5	5	100.00
		keymgr_csr_rw	2.720s	21.558us	14	20	70.00
		keymgr_csr_aliasing	6.870s	855.595us	4	5	80.00
		keymgr_same_csr_outstanding	4.470s	353.368us	14	20	70.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	2.610s	26.204us	5	5	100.00
		keymgr_csr_rw	2.720s	21.558us	14	20	70.00
		keymgr_csr_aliasing	6.870s	855.595us	4	5	80.00
		keymgr_same_csr_outstanding	4.470s	353.368us	14	20	70.00
V2		TOTAL			729	740	98.51
V2S	sec_cm_additional_check	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
		keymgr_tl_intg_err	7.820s	264.063us	15	20	75.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	6.660s	250.581us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	6.660s	250.581us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	6.660s	250.581us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	6.660s	250.581us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	13.910s	1.688ms	12	20	60.00
V2S	prim_count_check	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	7.820s	264.063us	15	20	75.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	6.660s	250.581us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.526m	2.626ms	48	50	96.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	49.620s	2.911ms	50	50	100.00
		keymgr_csr_rw	2.720s	21.558us	14	20	70.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	49.620s	2.911ms	50	50	100.00
		keymgr_csr_rw	2.720s	21.558us	14	20	70.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	49.620s	2.911ms	50	50	100.00
		keymgr_csr_rw	2.720s	21.558us	14	20	70.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.410s	275.138us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	39.830s	2.201ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	39.830s	2.201ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	49.620s	2.911ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	30.930s	1.272ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	15.140s	2.154ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.410s	275.138us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	15.140s	2.154ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	15.140s	2.154ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	15.140s	2.154ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	18.580s	969.354us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	15.140s	2.154ms	49	50	98.00
V2S		TOTAL			151	165	91.52
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.710s	625.141us	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			1053	1110	94.86

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.83	99.10	98.18	98.67	100.00	99.02	98.63	91.18

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 30 failures:

Test keymgr_csr_rw has 6 failures.

0.keymgr_csr_rw.8093170142448747240942117158798699179997451980480333835994730093689645726023
Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[10] & 'hffffffff)))'
  UVM_ERROR @  22180837 ps: (keymgr_csr_assert_fpv.sv:416) [ASSERT FAILED] sealing_sw_binding_5_rd_A
  UVM_INFO @  22180837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_csr_rw.79231307622834001279645570407556944181387967642662474707551467262052659533754
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[11] & 'hffffffff)))'
  UVM_ERROR @   3460383 ps: (keymgr_csr_assert_fpv.sv:421) [ASSERT FAILED] sealing_sw_binding_6_rd_A
  UVM_INFO @   3460383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_csr_bit_bash has 2 failures.

0.keymgr_csr_bit_bash.27493293430205530608162004787988419326068796788782173092275725544947126147998
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[7] & 'hffffffff)))'
  UVM_ERROR @ 364367432 ps: (keymgr_csr_assert_fpv.sv:401) [ASSERT FAILED] sealing_sw_binding_2_rd_A
  UVM_INFO @ 364367432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.keymgr_csr_bit_bash.94819307875931858345154758834106064847901249373079233251917216980496144389258
Line 75, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[14] & 'hffffffff)))'
  UVM_ERROR @ 313826019 ps: (keymgr_csr_assert_fpv.sv:436) [ASSERT FAILED] attest_sw_binding_1_rd_A
  UVM_INFO @ 313826019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_same_csr_outstanding has 6 failures.

0.keymgr_same_csr_outstanding.12060145553828156355768451652363417296636427919787327050386439704968846699700
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @ 495934178 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @ 495934178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.keymgr_same_csr_outstanding.52253381259317667211413724081824582986393837096959307867906123595320776358477
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[15] & 'hffffffff)))'
  UVM_ERROR @ 197877091 ps: (keymgr_csr_assert_fpv.sv:441) [ASSERT FAILED] attest_sw_binding_2_rd_A
  UVM_INFO @ 197877091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test keymgr_tl_intg_err has 5 failures.

1.keymgr_tl_intg_err.92510363126823221633909342428496353768996079654093506821347503543607033037290
Line 111, in log /nightly/runs/scratch/master/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[9] & 'hffffffff)))'
  UVM_ERROR @  81941315 ps: (keymgr_csr_assert_fpv.sv:411) [ASSERT FAILED] sealing_sw_binding_4_rd_A
  UVM_INFO @  81941315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.keymgr_tl_intg_err.49381435092550952271377253228665128657378165684052064540650158525653137289804
Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[12] & 'hffffffff)))'
  UVM_ERROR @  10160688 ps: (keymgr_csr_assert_fpv.sv:426) [ASSERT FAILED] sealing_sw_binding_7_rd_A
  UVM_INFO @  10160688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test keymgr_csr_aliasing has 1 failures.

2.keymgr_csr_aliasing.31728509915049824017610101083297810485784398712821723221494232700927450530947
Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[19] & 'hffffffff)))'
  UVM_ERROR @ 486888582 ps: (keymgr_csr_assert_fpv.sv:461) [ASSERT FAILED] attest_sw_binding_6_rd_A
  UVM_INFO @ 486888582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more tests.

UVM_ERROR (cip_base_vseq.sv:924) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 19 failures:
- Test keymgr_stress_all_with_rand_reset has 19 failures.
  - 4.keymgr_stress_all_with_rand_reset.61533421555955243523723302742743040847890620435609044747760868540726604126732
    Line 157, in log /nightly/runs/scratch/master/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1016252991 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1016252991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 5.keymgr_stress_all_with_rand_reset.107967131846624890291213395386696636643998425416145607548383779117751751161045
    Line 112, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 568085569 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 568085569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 17 more failures.

UVM_ERROR (cip_base_scoreboard.sv:349) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_stress_all has 2 failures.

2.keymgr_stress_all.76331163230292564416988381188453037035595055176793139186926494165076062990087
Line 354, in log /nightly/runs/scratch/master/keymgr-sim-vcs/2.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 2626383606 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 2626383606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.keymgr_stress_all.99912466642511856023897872744099995878409680966043633743712397337364465001576
Line 2747, in log /nightly/runs/scratch/master/keymgr-sim-vcs/23.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 767356115 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @ 767356115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sideload_kmac has 1 failures.

16.keymgr_sideload_kmac.88251375765327437581903241473950907427481918634955452657013381779350342669317
Line 85, in log /nightly/runs/scratch/master/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest/run.log

  UVM_ERROR @   4324845 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @   4324845 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_smoke has 1 failures.

49.keymgr_smoke.40465044641627463346207679731322540592371187929672890508350154576020360065601
Line 114, in log /nightly/runs/scratch/master/keymgr-sim-vcs/49.keymgr_smoke/latest/run.log

  UVM_ERROR @  28222357 ps: (cip_base_scoreboard.sv:349) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
  UVM_INFO @  28222357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data == gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 2 failures:

Test keymgr_cfg_regwen has 2 failures.

5.keymgr_cfg_regwen.57429450336527511334873922179731053077642399593733093410272348807656737449842
Line 259, in log /nightly/runs/scratch/master/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @  22765006 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @  22765006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.keymgr_cfg_regwen.574951127568966103204643095291116440784308138967667572046497253047219924261
Line 139, in log /nightly/runs/scratch/master/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest/run.log

  UVM_ERROR @   9605610 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
  UVM_INFO @   9605610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (keymgr_custom_cm_vseq.sv:40) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:
- Test keymgr_custom_cm has 1 failures.
  - 3.keymgr_custom_cm.19952835808762914398831650190479299074394382566498666279996652782345368092740
    Line 112, in log /nightly/runs/scratch/master/keymgr-sim-vcs/3.keymgr_custom_cm/latest/run.log
```
  UVM_FATAL @ 10265339936 ps: (keymgr_custom_cm_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
  UVM_INFO @ 10265339936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:828) [keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 24.keymgr_stress_all_with_rand_reset.101829225129698208577979722636687406865406490032219150330981072590764810858167
    Line 556, in log /nightly/runs/scratch/master/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 247988273 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 247988273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```