KMAC/MASKED Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.533m	34.189ms	49	50	98.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.470s	60.651us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.310s	28.494us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.440s	3.858ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.620s	1.925ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.540s	357.704us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.310s	28.494us	20	20	100.00
		kmac_csr_aliasing	8.620s	1.925ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	1.880s	13.109us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.470s	84.744us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	long_msg_and_output	kmac_long_msg_and_output	48.899m	518.380ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.148m	134.356ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	39.349m	95.390ms	5	5	100.00
		kmac_test_vectors_sha3_256	31.417m	75.517ms	5	5	100.00
		kmac_test_vectors_sha3_384	28.262m	351.689ms	5	5	100.00
		kmac_test_vectors_sha3_512	21.933m	195.600ms	5	5	100.00
		kmac_test_vectors_shake_128	31.270m	45.563ms	5	5	100.00
		kmac_test_vectors_shake_256	33.533m	302.303ms	5	5	100.00
		kmac_test_vectors_kmac	4.850s	125.245us	5	5	100.00
		kmac_test_vectors_kmac_xof	5.040s	118.856us	5	5	100.00
V2	sideload	kmac_sideload	8.710m	19.842ms	50	50	100.00
V2	app	kmac_app	6.662m	13.052ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.435m	32.421ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.465m	35.616ms	50	50	100.00
V2	error	kmac_error	7.003m	69.685ms	50	50	100.00
V2	key_error	kmac_key_error	20.220s	7.052ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	11.240s	2.059ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	44.740s	644.734us	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	39.410s	560.931us	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.406m	53.289ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	25.510s	1.785ms	50	50	100.00
V2	stress_all	kmac_stress_all	42.637m	99.664ms	49	50	98.00
V2	intr_test	kmac_intr_test	2.170s	23.695us	50	50	100.00
V2	alert_test	kmac_alert_test	2.380s	23.531us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.260s	688.164us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.260s	688.164us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.470s	60.651us	5	5	100.00
		kmac_csr_rw	2.310s	28.494us	20	20	100.00
		kmac_csr_aliasing	8.620s	1.925ms	5	5	100.00
		kmac_same_csr_outstanding	3.530s	1.872ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.470s	60.651us	5	5	100.00
		kmac_csr_rw	2.310s	28.494us	20	20	100.00
		kmac_csr_aliasing	8.620s	1.925ms	5	5	100.00
		kmac_same_csr_outstanding	3.530s	1.872ms	20	20	100.00
V2		TOTAL			739	740	99.86
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.990s	105.687us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.990s	105.687us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.990s	105.687us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.990s	105.687us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.560s	1.275ms	11	20	55.00
V2S	tl_intg_err	kmac_sec_cm	1.977m	10.584ms	5	5	100.00
		kmac_tl_intg_err	4.960s	748.721us	17	20	85.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	4.960s	748.721us	17	20	85.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	25.510s	1.785ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.533m	34.189ms	49	50	98.00
V2S	sec_cm_key_sideload	kmac_sideload	8.710m	19.842ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.990s	105.687us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.977m	10.584ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.977m	10.584ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.977m	10.584ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.533m	34.189ms	49	50	98.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	25.510s	1.785ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.977m	10.584ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.586m	68.021ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.533m	34.189ms	49	50	98.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	5.206m	8.927ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			923	940	98.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.43	99.09	94.43	99.51	80.99	97.05	99.06	97.86

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 11 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 8 failures.

0.kmac_shadow_reg_errors_with_csr_rw.86136664174847742403188703726366683537050368639213444055274312693807662718641
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  29378221 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  29378221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_shadow_reg_errors_with_csr_rw.29614755616718182548945613594611907040011141562281991122799587511672693526675
Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  53519521 ps: (kmac_csr_assert_fpv.sv:497) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  53519521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test kmac_tl_intg_err has 3 failures.

0.kmac_tl_intg_err.74673423955775874925586086430982262308766116613966869673887610952694366917467
Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[45] & 'hffffffff)))'
  UVM_ERROR @  13351083 ps: (kmac_csr_assert_fpv.sv:522) [ASSERT FAILED] prefix_6_rd_A
  UVM_INFO @  13351083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.kmac_tl_intg_err.85428192247160841125019827172344835969449528539132650307504286653934416269445
Line 90, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
  UVM_ERROR @  85279022 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
  UVM_INFO @  85279022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 3 failures:
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 2.kmac_stress_all_with_rand_reset.22215889163194966162154444798835234059686857770269000730420456974108162923297
    Line 118, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2051081315 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 2051081315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 3.kmac_stress_all_with_rand_reset.48978562325213918932778228992848289164897497994623345961651622455278440576470
    Line 129, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9507058815 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 9507058815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 2 failures:
- Test kmac_stress_all has 1 failures.
  - 13.kmac_stress_all.42183699077791891780042377018862905361861913172148540471250786489416299667959
    Line 368, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/13.kmac_stress_all/latest/run.log
```
  UVM_ERROR @ 62094270200 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 62094270200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_smoke has 1 failures.
  - 35.kmac_smoke.309094584107705466173784327003274811317373869018127130610561428531952302906
    Line 72, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/35.kmac_smoke/latest/run.log
```
  UVM_ERROR @  73909876 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  73909876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 12.kmac_shadow_reg_errors_with_csr_rw.50717867289411556218240085918157074583316601062801885196888442237559433617858
    Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  43963766 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (607395107 [0x24341d23] vs 0 [0x0]) Regname: kmac_reg_block.prefix_10 reset value: 0x0
  UVM_INFO @  43963766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```