KMAC/UNMASKED Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.097m	7.106ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.730s	85.854us	5	5	100.00
V1	csr_rw	kmac_csr_rw	2.520s	56.641us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.200s	1.011ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	8.920s	402.328us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.260s	264.573us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	2.520s	56.641us	20	20	100.00
		kmac_csr_aliasing	8.920s	402.328us	5	5	100.00
V1	mem_walk	kmac_mem_walk	2.330s	23.853us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.930s	32.804us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	43.723m	150.713ms	50	50	100.00
V2	burst_write	kmac_burst_write	15.974m	51.396ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.119m	82.947ms	5	5	100.00
		kmac_test_vectors_sha3_256	25.453m	59.873ms	5	5	100.00
		kmac_test_vectors_sha3_384	27.900s	1.262ms	5	5	100.00
		kmac_test_vectors_sha3_512	16.238m	129.838ms	5	5	100.00
		kmac_test_vectors_shake_128	26.405m	20.653ms	5	5	100.00
		kmac_test_vectors_shake_256	20.430m	152.753ms	5	5	100.00
		kmac_test_vectors_kmac	4.290s	287.208us	5	5	100.00
		kmac_test_vectors_kmac_xof	3.810s	128.569us	5	5	100.00
V2	sideload	kmac_sideload	6.678m	316.694ms	50	50	100.00
V2	app	kmac_app	4.667m	52.334ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.838m	17.578ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.815m	53.977ms	50	50	100.00
V2	error	kmac_error	5.951m	70.098ms	49	50	98.00
V2	key_error	kmac_key_error	13.460s	16.884ms	50	50	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.270m	10.072ms	39	50	78.00
V2	edn_timeout_error	kmac_edn_timeout_error	34.710s	3.704ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.040s	10.551ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.194m	39.655ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.530s	3.843ms	50	50	100.00
V2	stress_all	kmac_stress_all	33.813m	99.066ms	50	50	100.00
V2	intr_test	kmac_intr_test	2.350s	30.406us	50	50	100.00
V2	alert_test	kmac_alert_test	2.340s	42.512us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.810s	322.990us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.810s	322.990us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.730s	85.854us	5	5	100.00
		kmac_csr_rw	2.520s	56.641us	20	20	100.00
		kmac_csr_aliasing	8.920s	402.328us	5	5	100.00
		kmac_same_csr_outstanding	3.870s	117.491us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.730s	85.854us	5	5	100.00
		kmac_csr_rw	2.520s	56.641us	20	20	100.00
		kmac_csr_aliasing	8.920s	402.328us	5	5	100.00
		kmac_same_csr_outstanding	3.870s	117.491us	20	20	100.00
V2		TOTAL			728	740	98.38
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.920s	706.788us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.920s	706.788us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.920s	706.788us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.920s	706.788us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.690s	548.784us	15	20	75.00
V2S	tl_intg_err	kmac_sec_cm	1.397m	9.711ms	5	5	100.00
		kmac_tl_intg_err	6.170s	201.855us	13	20	65.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.170s	201.855us	13	20	65.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.530s	3.843ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.097m	7.106ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.678m	316.694ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.920s	706.788us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.397m	9.711ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.397m	9.711ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.397m	9.711ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.097m	7.106ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.530s	3.843ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.397m	9.711ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.853m	87.116ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.097m	7.106ms	50	50	100.00
V2S		TOTAL			63	75	84.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	4.000m	27.787ms	7	10	70.00
V3		TOTAL			7	10	70.00
		TOTAL			913	940	97.13

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
93.65	97.18	94.42	100.00	72.73	95.93	99.02	96.27

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 12 failures:

Test kmac_tl_intg_err has 7 failures.

0.kmac_tl_intg_err.17812203771692806213500524608166465145524411651989292662903544132342602596640
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[44] & 'hffffffff)))'
  UVM_ERROR @   9195947 ps: (kmac_csr_assert_fpv.sv:517) [ASSERT FAILED] prefix_5_rd_A
  UVM_INFO @   9195947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.kmac_tl_intg_err.19381571915211697200559820825326993549539427494832371981286272886568597471484
Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
  UVM_ERROR @  18786408 ps: (kmac_csr_assert_fpv.sv:512) [ASSERT FAILED] prefix_4_rd_A
  UVM_INFO @  18786408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test kmac_shadow_reg_errors_with_csr_rw has 5 failures.

6.kmac_shadow_reg_errors_with_csr_rw.90523543457775905240808498868214657215890979076206043711332027418293581517797
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffff03ff) == (exp_vals[4] & 'hffff03ff)))'
  UVM_ERROR @  64600602 ps: (kmac_csr_assert_fpv.sv:487) [ASSERT FAILED] entropy_period_rd_A
  UVM_INFO @  64600602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.kmac_shadow_reg_errors_with_csr_rw.57417753483317243311560877852981135799233015708673716864219179259808181592539
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
  UVM_ERROR @   6847673 ps: (kmac_csr_assert_fpv.sv:507) [ASSERT FAILED] prefix_3_rd_A
  UVM_INFO @   6847673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 3 failures:
- Test kmac_sideload_invalid has 3 failures.
  - 11.kmac_sideload_invalid.86496335583083634466654354820060631962208785459018486493392000875159873726973
    Line 76, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/11.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10014407777 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xf2da1000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10014407777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 26.kmac_sideload_invalid.78024837446766823281596568038819646708415007706950996146275878227822653189669
    Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/26.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10112929881 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xacb01000, Comparison=CompareOpEq, exp_data=0x1, call_count=4)
  UVM_INFO @ 10112929881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 2 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 0.kmac_stress_all_with_rand_reset.71851532086928470978354017549191583834533400335869692255594602572425724103187
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  67334308 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @  67334308 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.kmac_stress_all_with_rand_reset.101775671581119877149125205248813568225363497023675631144929675976639823775058
    Line 90, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 130533956 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 130533956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 2 failures:
- Test kmac_sideload_invalid has 2 failures.
  - 33.kmac_sideload_invalid.104472914074353368264813732499476488528735825020446096620253242895560162404672
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/33.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10211355441 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x2c203000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10211355441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 49.kmac_sideload_invalid.69783704657348443621567768488744543222008651700672985549227576726642875086645
    Line 80, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/49.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10290750165 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x65580000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
  UVM_INFO @ 10290750165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_error has 1 failures.
  - 0.kmac_error.45388221286264329565779726188627039956001893764425666254394730719518110694022
    Line 202, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_error/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:924) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 6.kmac_stress_all_with_rand_reset.39534559330592978982139874386148381595793821754003147239332815983844643850248
    Line 96, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2154798470 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 100000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2154798470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=24) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 19.kmac_sideload_invalid.70420949301475075092847721619191200270629364475089981380312001077973515677680
    Line 97, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/19.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10199119572 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xbf5da000, Comparison=CompareOpEq, exp_data=0x1, call_count=24)
  UVM_INFO @ 10199119572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 28.kmac_sideload_invalid.30110057537525147646276321857880242831964542241148480506324076850840636205079
    Line 77, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/28.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10038011418 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x4197000, Comparison=CompareOpEq, exp_data=0x1, call_count=5)
  UVM_INFO @ 10038011418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 29.kmac_sideload_invalid.19169107683611602643527278771588411407232965519534983152400152465928862815080
    Line 73, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/29.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10011959833 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xe9e6b000, Comparison=CompareOpEq, exp_data=0x1, call_count=2)
  UVM_INFO @ 10011959833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 38.kmac_sideload_invalid.44089374104433833393808060880721284284467891333494591677570468060564330088817
    Line 85, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/38.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10071959675 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x10293000, Comparison=CompareOpEq, exp_data=0x1, call_count=11)
  UVM_INFO @ 10071959675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 39.kmac_sideload_invalid.5510873052861045879528359925129228457274591801066910263878305444990573937206
    Line 79, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/39.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10128367682 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0x6de13000, Comparison=CompareOpEq, exp_data=0x1, call_count=7)
  UVM_INFO @ 10128367682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 40.kmac_sideload_invalid.16030912503394000378989644971294653604081928065877644148130841882650102651764
    Line 96, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/40.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10223282562 ps: (csr_utils_pkg.sv:624) [csr_utils::csr_spinwait] timeout kmac_reg_block.intr_state.kmac_done (addr=0xcb289000, Comparison=CompareOpEq, exp_data=0x1, call_count=22)
  UVM_INFO @ 10223282562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```