OTBN Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	14.000s	305.022us	1	1	100.00
V1	single_binary	otbn_single	1.283m	380.186us	100	100	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	13.000s	57.342us	5	5	100.00
V1	csr_rw	otbn_csr_rw	8.000s	15.634us	20	20	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	11.000s	35.899us	5	5	100.00
V1	csr_aliasing	otbn_csr_aliasing	7.000s	27.516us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	13.000s	38.644us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	8.000s	15.634us	20	20	100.00
		otbn_csr_aliasing	7.000s	27.516us	5	5	100.00
V1	mem_walk	otbn_mem_walk	50.000s	915.226us	5	5	100.00
V1	mem_partial_access	otbn_mem_partial_access	24.000s	474.205us	5	5	100.00
V1		TOTAL			166	166	100.00
V2	reset_recovery	otbn_reset	13.133m	5.043ms	10	10	100.00
V2	multi_error	otbn_multi_err	1.050m	607.727us	1	1	100.00
V2	back_to_back	otbn_multi	1.383m	1.908ms	9	10	90.00
V2	stress_all	otbn_stress_all	1.550m	292.522us	10	10	100.00
V2	lc_escalation	otbn_escalate	53.000s	1.040ms	59	60	98.33
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	9.000s	16.962us	5	5	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	53.237us	10	10	100.00
V2	alert_test	otbn_alert_test	12.000s	31.724us	50	50	100.00
V2	intr_test	otbn_intr_test	32.000s	13.065us	50	50	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	45.000s	347.061us	20	20	100.00
V2	tl_d_illegal_access	otbn_tl_errors	45.000s	347.061us	20	20	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	13.000s	57.342us	5	5	100.00
		otbn_csr_rw	8.000s	15.634us	20	20	100.00
		otbn_csr_aliasing	7.000s	27.516us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	50.100us	20	20	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	13.000s	57.342us	5	5	100.00
		otbn_csr_rw	8.000s	15.634us	20	20	100.00
		otbn_csr_aliasing	7.000s	27.516us	5	5	100.00
		otbn_same_csr_outstanding	9.000s	50.100us	20	20	100.00
V2		TOTAL			244	246	99.19
V2S	mem_integrity	otbn_imem_err	14.000s	29.123us	10	10	100.00
		otbn_dmem_err	24.000s	45.643us	15	15	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	135.584us	5	5	100.00
		otbn_controller_ispr_rdata_err	16.000s	75.288us	5	5	100.00
		otbn_mac_bignum_acc_err	17.000s	46.961us	5	5	100.00
		otbn_urnd_err	12.000s	29.036us	2	2	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	11.000s	69.029us	5	5	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	10.000s	34.327us	2	2	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	11.000s	26.260us	9	10	90.00
V2S	tl_intg_err	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
		otbn_tl_intg_err	51.000s	84.275us	20	20	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	1.167m	663.614us	17	20	85.00
V2S	prim_fsm_check	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	prim_count_check	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_mem_scramble	otbn_smoke	14.000s	305.022us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	24.000s	45.643us	15	15	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	14.000s	29.123us	10	10	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	51.000s	84.275us	20	20	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	53.000s	1.040ms	59	60	98.33
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	14.000s	29.123us	10	10	100.00
		otbn_dmem_err	24.000s	45.643us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.962us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	69.029us	5	5	100.00
		otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_scramble_key_sideload	otbn_single	1.283m	380.186us	100	100	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	14.000s	29.123us	10	10	100.00
		otbn_dmem_err	24.000s	45.643us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.962us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	69.029us	5	5	100.00
		otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	53.000s	1.040ms	59	60	98.33
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	14.000s	29.123us	10	10	100.00
		otbn_dmem_err	24.000s	45.643us	15	15	100.00
		otbn_zero_state_err_urnd	9.000s	16.962us	5	5	100.00
		otbn_illegal_mem_acc	11.000s	69.029us	5	5	100.00
		otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	1.283m	380.186us	100	100	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	35.562us	12	12	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	12.000s	73.881us	5	5	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	1.033m	1.527ms	5	5	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	1.033m	1.527ms	5	5	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	25.000s	85.053us	10	10	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	14.000s	116.612us	10	10	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	23.774us	4	5	80.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	11.000s	23.774us	4	5	80.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	21.000s	78.125us	5	7	71.43
V2S	sec_cm_data_mem_sec_wipe	otbn_single	1.283m	380.186us	100	100	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	1.283m	380.186us	100	100	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	1.283m	380.186us	100	100	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	1.383m	1.908ms	9	10	90.00
V2S	sec_cm_ctrl_flow_count	otbn_single	1.283m	380.186us	100	100	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	1.283m	380.186us	100	100	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	1.450m	386.899us	4	5	80.00
V2S	sec_cm_key_sideload	otbn_single	1.283m	380.186us	100	100	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	6.633m	2.552ms	3	5	60.00
V2S		TOTAL			153	163	93.87
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	5.567m	9.266ms	5	10	50.00
V3		TOTAL			5	10	50.00
		TOTAL			568	585	97.09

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
99.04	99.64	96.01	99.72	93.32	93.41	97.44	90.90	100.00

Failure Buckets

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 4 failures:

Test otbn_sec_wipe_err has 2 failures.

0.otbn_sec_wipe_err.29870622971222864813481840727366431018469309586367435029088156825849944339444
Line 109, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 39081522 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  39081522 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  39081522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_wipe_err.32142648202217497855882295139232905329613191549317789226802249924319887468312
Line 117, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_wipe_err/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 78125251 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  78125251 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  78125251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_stack_addr_integ_chk has 1 failures.

1.otbn_stack_addr_integ_chk.66622189565032308067980086903266832779703619988176599790471285769854816105675
Line 116, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stack_addr_integ_chk/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 6391896 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,137): (time 6391896 PS) Assertion tb.model_if.NoModelErrs has failed
  UVM_ERROR @   6391896 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @   6391896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_escalate has 1 failures.

31.otbn_escalate.58345078473872334481554732756989417978695657209990697167775602629888444790748
Line 114, in log /nightly/runs/scratch/master/otbn-sim-xcelium/31.otbn_escalate/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 39191156 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
  UVM_ERROR @  39191156 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
  UVM_INFO @  39191156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:925) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 3 failures:
- Test otbn_stress_all_with_rand_reset has 3 failures.
  - 1.otbn_stress_all_with_rand_reset.68819765933211543550069492978714439284403354687912110815937086843924343235917
    Line 157, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 124428336 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 124428336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.otbn_stress_all_with_rand_reset.57732916074829863918673711039955771778625349707352618910354887257724568437512
    Line 194, in log /nightly/runs/scratch/master/otbn-sim-xcelium/2.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 231605723 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 231605723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. has 3 failures:

Test otbn_sw_no_acc has 1 failures.

4.otbn_sw_no_acc.38857503110042867274553553435771085516801661126257814097147176064569979274853
Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/4.otbn_sw_no_acc/latest/run.log

  UVM_FATAL @  20176001 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @  20176001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_passthru_mem_tl_intg_err has 1 failures.

6.otbn_passthru_mem_tl_intg_err.4240355752001144788887657370499057663504051061416132930240987393829816673574
Line 82, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_passthru_mem_tl_intg_err/latest/run.log

  UVM_FATAL @   5470536 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @   5470536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test otbn_multi has 1 failures.

8.otbn_multi.31474579527196629961855153400593428873242239966557981584209487916081184549688
Line 143, in log /nightly/runs/scratch/master/otbn-sim-xcelium/8.otbn_multi/latest/run.log

  UVM_FATAL @ 193731147 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a recov alert but it still hasn't arrived.
  UVM_INFO @ 193731147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_*/rtl/otbn.sv,1383): Assertion ErrBitsKnown_A has failed has 2 failures:

Test otbn_sec_cm has 2 failures.

0.otbn_sec_cm.108244041828964883057371956699692698919501505157580026345818470868498292874834
Line 118, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 132827594 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 132827594 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @ 132827594 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @ 132827594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.otbn_sec_cm.4438830443499270870979516613474585404324820333580862088055861356284267736857
Line 125, in log /nightly/runs/scratch/master/otbn-sim-xcelium/1.otbn_sec_cm/latest/run.log

  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn.sv,1383): (time 52363387 PS) Assertion tb.dut.ErrBitsKnown_A has failed
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_ip_otbn_0.1/rtl/otbn_core.sv,960): (time 52363387 PS) Assertion tb.dut.u_otbn_core.ErrBitsKnown_A has failed
  UVM_ERROR @  52363387 ps: (otbn.sv:1383) [ASSERT FAILED] ErrBitsKnown_A
  UVM_INFO @  52363387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 2 failures:
- Test otbn_passthru_mem_tl_intg_err has 2 failures.
  - 11.otbn_passthru_mem_tl_intg_err.42337977835034372378252661738338332490681823467294221699199740799182773147071
    Line 92, in log /nightly/runs/scratch/master/otbn-sim-xcelium/11.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @  20525677 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @  20525677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 12.otbn_passthru_mem_tl_intg_err.73984932197799790798969028901733587992081072206137076885780702362444546219885
    Line 117, in log /nightly/runs/scratch/master/otbn-sim-xcelium/12.otbn_passthru_mem_tl_intg_err/latest/run.log
```
  UVM_FATAL @ 377042134 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
  UVM_INFO @ 377042134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 5.otbn_stress_all_with_rand_reset.1084527902386599737159501171327508657955844090321691641790798517434280447681
    Line 153, in log /nightly/runs/scratch/master/otbn-sim-xcelium/5.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  15688644 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @  15688644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (otbn_base_vseq.sv:348) [otbn_imem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:
- Test otbn_stress_all_with_rand_reset has 1 failures.
  - 6.otbn_stress_all_with_rand_reset.67188169183164761176399595460037580769469485501419496480214822231412288339797
    Line 291, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1721813018 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_imem_err_vseq] Check failed (!cfg.under_reset)
  UVM_INFO @ 1721813018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_*/tb.sv,292): Assertion MatchingStatus_A has failed has 1 failures:
- Test otbn_partial_wipe has 1 failures.
  - 6.otbn_partial_wipe.69214381316755679747056921193177616485224623209129052309313288383347768877192
    Line 104, in log /nightly/runs/scratch/master/otbn-sim-xcelium/6.otbn_partial_wipe/latest/run.log
```
  xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_sim_0.1/tb.sv,292): (time 3465952 PS) Assertion tb.MatchingStatus_A has failed
  UVM_ERROR @   3465952 ps: (tb.sv:292) [ASSERT FAILED] MatchingStatus_A
  UVM_INFO @   3465952 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```