97d23b4| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pattgen_smoke | 48.000s | 38.816us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pattgen_csr_hw_reset | 5.000s | 15.839us | 5 | 5 | 100.00 |
| V1 | csr_rw | pattgen_csr_rw | 5.000s | 61.015us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pattgen_csr_bit_bash | 6.000s | 787.234us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pattgen_csr_aliasing | 5.000s | 126.485us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pattgen_csr_mem_rw_with_rand_reset | 5.000s | 47.034us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pattgen_csr_rw | 5.000s | 61.015us | 20 | 20 | 100.00 |
| pattgen_csr_aliasing | 5.000s | 126.485us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | perf | pattgen_perf | 1.950m | 2.776ms | 50 | 50 | 100.00 |
| V2 | cnt_rollover | cnt_rollover | 1.900m | 41.191ms | 50 | 50 | 100.00 |
| V2 | error | pattgen_error | 48.000s | 54.195us | 50 | 50 | 100.00 |
| V2 | stress_all | pattgen_stress_all | 1.983m | 4.127ms | 25 | 50 | 50.00 |
| V2 | alert_test | pattgen_alert_test | 48.000s | 32.198us | 50 | 50 | 100.00 |
| V2 | intr_test | pattgen_intr_test | 5.000s | 97.123us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pattgen_tl_errors | 7.000s | 2.177ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pattgen_tl_errors | 7.000s | 2.177ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pattgen_csr_hw_reset | 5.000s | 15.839us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 61.015us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 126.485us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 79.221us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pattgen_csr_hw_reset | 5.000s | 15.839us | 5 | 5 | 100.00 |
| pattgen_csr_rw | 5.000s | 61.015us | 20 | 20 | 100.00 | ||
| pattgen_csr_aliasing | 5.000s | 126.485us | 5 | 5 | 100.00 | ||
| pattgen_same_csr_outstanding | 5.000s | 79.221us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 315 | 340 | 92.65 | |||
| V2S | tl_intg_err | pattgen_tl_intg_err | 5.000s | 116.468us | 20 | 20 | 100.00 |
| pattgen_sec_cm | 48.000s | 2.167ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pattgen_tl_intg_err | 5.000s | 116.468us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | pattgen_stress_all_with_rand_reset | 2.000m | 19.173ms | 2 | 50 | 4.00 |
| V3 | TOTAL | 2 | 50 | 4.00 | |||
| Unmapped tests | pattgen_inactive_level | 4.400m | 10.002ms | 28 | 50 | 56.00 | |
| TOTAL | 475 | 570 | 83.33 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.88 | 100.00 | 100.00 | 100.00 | 98.50 | 96.61 | -- | 100.00 | 90.73 |
UVM_ERROR (cip_base_vseq.sv:925) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:
0.pattgen_stress_all_with_rand_reset.110963260367788340190580968864310994651359316217514667129155112041002917619430
Line 176, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1898404512 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1898415149 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1898415149 ps: (cip_base_vseq.sv:832) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 2/10
UVM_INFO @ 1898455965 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
1.pattgen_stress_all_with_rand_reset.59186079984637220054786107043821290468413568896913042391792512937405131462995
Line 237, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1498727485 ps: (cip_base_vseq.sv:925) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 1498733424 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1498733424 ps: (cip_base_vseq.sv:832) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 4/10
UVM_INFO @ 1498807106 ps: (cip_base_vseq.sv:853) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
... and 45 more failures.
UVM_ERROR (pattgen_scoreboard.sv:76) [scoreboard] exp_item_q[i] item uncompared: has 25 failures:
0.pattgen_stress_all.95115719891915002616913113279051579182955714078685313216931567333184887516322
Line 141, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all/latest/run.log
UVM_ERROR @ 5625209298 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @11389
1.pattgen_stress_all.84926239774723666378091583689598349985025639961771834152282869810103695242021
Line 145, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_stress_all/latest/run.log
UVM_ERROR @ 5832024937 ps: (pattgen_scoreboard.sv:76) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
------------------------------------
Name Type Size Value
------------------------------------
exp_item pattgen_item - @10148
... and 23 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 4 failures:
1.pattgen_inactive_level.49569051028165794577123418641994799071713893472027033723888393093000824353973
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10159458909 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xade2d890, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10159458909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.pattgen_inactive_level.64552536039849589146799718867521602532810971841051951105947884248950623653791
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10003228750 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdb6c8a10, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
UVM_INFO @ 10003228750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 4 failures:
6.pattgen_inactive_level.91387903056500009209091355697388468685895272510489373514456574830836081880493
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10009949671 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf00aead0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10009949671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.pattgen_inactive_level.111621962806798378899256839884582152083962029314038702446524354345156690507124
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10004505610 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xab2fd490, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
UVM_INFO @ 10004505610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 3 failures:
7.pattgen_inactive_level.50842503348101224908632723794236123590304066785631125631530543669288188746119
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10005265039 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcd6189d0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10005265039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pattgen_inactive_level.103474587242439859842336283390718720986635352887570868452747836035289431763257
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10013344963 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe2e73d10, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
UVM_INFO @ 10013344963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 2 failures:
12.pattgen_inactive_level.99197858658327666526869038839268113642744467652257186289579998018984678638154
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/12.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10023737480 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xf48a51d0, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10023737480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.pattgen_inactive_level.28448206743593093655303734097718807335301571656549848730320576637255424655595
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10002342879 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x607d3810, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
UVM_INFO @ 10002342879 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
16.pattgen_inactive_level.49537073704304551323163912484062024234596576459666024984262264288622838296065
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10012112100 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xca64ed10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10012112100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.pattgen_inactive_level.43128022191159974121502270703778189547780468211810572204870241492483892287565
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/38.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10015139947 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe56bce10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
UVM_INFO @ 10015139947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
28.pattgen_inactive_level.14978148927041903830002567638829286681023229811003351876082250682668917942837
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10017103675 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb4c77310, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10017103675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.pattgen_inactive_level.57942144466768988096246041409780523771380013254988856068976148732536457453550
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10343214349 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xab916690, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
UVM_INFO @ 10343214349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
10.pattgen_inactive_level.57914566249434129680824342101546765183116669510099481612977457185766131890268
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10115269712 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfc6d95d0, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
UVM_INFO @ 10115269712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
22.pattgen_inactive_level.42013249708089639764075009986348643399843355339570278348123078078138513592888
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10044604410 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xdcf8e790, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
UVM_INFO @ 10044604410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (pattgen_scoreboard.sv:263) scoreboard [scoreboard] has 1 failures:
30.pattgen_stress_all_with_rand_reset.51060138906646541519400730713503675379071128956995033996318237059795770514167
Line 118, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 258419082 ps: (pattgen_scoreboard.sv:263) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
--> channel 1 item mismatch!
--> EXP:
------------------------------------
Name Type Size Value
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
36.pattgen_inactive_level.34479957166809598135695750416519245040658748502745403874651115471422810562873
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10010323594 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xf083f990, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
UVM_INFO @ 10010323594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
42.pattgen_inactive_level.14972517886451165427175193131762404569658644939520385142506149529541491369381
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10116866083 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xeee87450, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
UVM_INFO @ 10116866083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
49.pattgen_inactive_level.41889180024771220694027789006042929992706877313920503419994703157522926591524
Line 96, in log /nightly/runs/scratch/master/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
UVM_FATAL @ 10145288823 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6b1e2410, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
UVM_INFO @ 10145288823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---