ROM_CTRL/32KB Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	5.630s	1.066ms	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.730s	396.193us	5	5	100.00
V1	csr_rw	rom_ctrl_csr_rw	8.190s	169.853us	20	20	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	8.280s	176.249us	5	5	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	8.230s	170.315us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	10.010s	556.152us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	8.190s	169.853us	20	20	100.00
		rom_ctrl_csr_aliasing	8.230s	170.315us	5	5	100.00
V1	mem_walk	rom_ctrl_mem_walk	6.650s	170.325us	5	5	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	8.000s	171.950us	5	5	100.00
V1		TOTAL			67	67	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	6.160s	136.563us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	27.770s	4.207ms	20	20	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	10.530s	377.223us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	7.790s	188.293us	50	50	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	11.020s	555.676us	20	20	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	11.020s	555.676us	20	20	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.730s	396.193us	5	5	100.00
		rom_ctrl_csr_rw	8.190s	169.853us	20	20	100.00
		rom_ctrl_csr_aliasing	8.230s	170.315us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.830s	181.015us	20	20	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.730s	396.193us	5	5	100.00
		rom_ctrl_csr_rw	8.190s	169.853us	20	20	100.00
		rom_ctrl_csr_aliasing	8.230s	170.315us	5	5	100.00
		rom_ctrl_same_csr_outstanding	8.830s	181.015us	20	20	100.00
V2		TOTAL			114	114	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	33.690s	2.571ms	20	20	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	3.801m	1.031ms	5	5	100.00
		rom_ctrl_tl_intg_err	59.230s	595.121us	20	20	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	3.801m	1.031ms	5	5	100.00
V2S	prim_count_check	rom_ctrl_sec_cm	3.801m	1.031ms	5	5	100.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	3.801m	1.031ms	5	5	100.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	3.801m	1.031ms	5	5	100.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	5.630s	1.066ms	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	5.630s	1.066ms	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	5.630s	1.066ms	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	59.230s	595.121us	20	20	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
		rom_ctrl_kmac_err_chk	10.530s	377.223us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	3.591m	46.113ms	16	20	80.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	33.690s	2.571ms	20	20	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	3.801m	1.031ms	5	5	100.00
V2S		TOTAL			61	65	93.85
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	9.752m	11.738ms	20	20	100.00
V3		TOTAL			20	20	100.00
		TOTAL			262	266	98.50

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.60	100.00	99.41	100.00	100.00	100.00	98.97	98.81

Failure Buckets

• UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:305) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True) has 4 failures:
  • Test rom_ctrl_corrupt_sig_fatal_chk has 4 failures.

    • 0.rom_ctrl_corrupt_sig_fatal_chk.18776124948994127384771038999981558883524240432631397809115995601585287378620
      Line 81, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 553192436 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:305) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 553192436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 4.rom_ctrl_corrupt_sig_fatal_chk.69220926541552161779079950837424116285239811621600612246234039162607312768035
      Line 87, in log /nightly/runs/scratch/master/rom_ctrl_32kB-sim-vcs/4.rom_ctrl_corrupt_sig_fatal_chk/latest/run.log

        UVM_ERROR @ 1195470363 ps: (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:305) [uvm_test_top.env.virtual_sequencer.rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
        UVM_INFO @ 1195470363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.