RV_TIMER Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	38.793m	568.238ms	200	200	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	2.200s	16.120us	5	5	100.00
V1	csr_rw	rv_timer_csr_rw	2.240s	15.219us	20	20	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	5.050s	572.609us	5	5	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	2.480s	66.236us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	3.320s	143.241us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	2.240s	15.219us	20	20	100.00
		rv_timer_csr_aliasing	2.480s	66.236us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	random_reset	rv_timer_random_reset	19.766m	180.892ms	50	50	100.00
V2	disabled	rv_timer_disabled	6.034m	166.123ms	46	50	92.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	21.382m	2.887s	50	50	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	21.382m	2.887s	50	50	100.00
V2	stress	rv_timer_stress_all	1.307h	4.556s	50	50	100.00
V2	intr_test	rv_timer_intr_test	2.240s	31.459us	50	50	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	4.490s	2.185ms	20	20	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	4.490s	2.185ms	20	20	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	2.200s	16.120us	5	5	100.00
		rv_timer_csr_rw	2.240s	15.219us	20	20	100.00
		rv_timer_csr_aliasing	2.480s	66.236us	5	5	100.00
		rv_timer_same_csr_outstanding	2.480s	35.438us	20	20	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	2.200s	16.120us	5	5	100.00
		rv_timer_csr_rw	2.240s	15.219us	20	20	100.00
		rv_timer_csr_aliasing	2.480s	66.236us	5	5	100.00
		rv_timer_same_csr_outstanding	2.480s	35.438us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	rv_timer_sec_cm	2.170s	357.545us	5	5	100.00
		rv_timer_tl_intg_err	3.170s	452.337us	20	20	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	3.170s	452.337us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	1.007m	4.382ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			583	620	94.03

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.17	99.65	99.08	92.06	--	99.13	99.68	99.43

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:924) [rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
  • Test rv_timer_stress_all_with_rand_reset has 31 failures.

    • 0.rv_timer_stress_all_with_rand_reset.86768075169931606811491355795992426226342526289114709737239544971228584159779
      Line 187, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/0.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6014808637 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6014808637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 1.rv_timer_stress_all_with_rand_reset.87882110226998086587842458532624054707073260650785229423718034832129546099391
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/1.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 422995044 ps: (cip_base_vseq.sv:924) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 422995044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 29 more failures.

• UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
  • Test rv_timer_disabled has 4 failures.

    • 2.rv_timer_disabled.62011435333048555807910857641896530125051595992129071475519487486645132507774
      Line 75, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/2.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 22.rv_timer_disabled.113053736792453403428156107987178281701633672164585091868268969595578386284750
      Line 72, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/22.rv_timer_disabled/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 2 more failures.

• UVM_ERROR (cip_base_vseq.sv:828) [rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 2 failures:
  • Test rv_timer_stress_all_with_rand_reset has 2 failures.

    • 29.rv_timer_stress_all_with_rand_reset.58938133046718575375951821451562904754280298211505166931523927564570619636089
      Line 90, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/29.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 972415040 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 972415040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 37.rv_timer_stress_all_with_rand_reset.45801094461207779218314837771327122669358928738118339880979508777618853122166
      Line 110, in log /nightly/runs/scratch/master/rv_timer-sim-vcs/37.rv_timer_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 17357278240 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 17357278240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---