SPI_DEVICE/1R1W Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	4.569m	53.878ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.730s	63.920us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	4.330s	121.345us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	38.170s	10.816ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	18.580s	4.019ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.110s	138.613us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	4.330s	121.345us	20	20	100.00
		spi_device_csr_aliasing	18.580s	4.019ms	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.160s	10.253us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.350s	65.502us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.390s	14.526us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.240s	1.381us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	2.140s	1.700us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	11.790s	325.342us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	11.790s	325.342us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	27.960s	26.537ms	50	50	100.00
		spi_device_tpm_sts_read	2.670s	117.055us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	46.970s	16.984ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	26.070s	11.797ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	52.700s	252.116ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	52.700s	252.116ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	27.680s	6.453ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	27.680s	6.453ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	27.680s	6.453ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	27.680s	6.453ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	27.680s	6.453ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	52.230s	48.098ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.662m	10.029ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.662m	10.029ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.662m	10.029ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	57.130s	3.887ms	50	50	100.00
		spi_device_read_buffer_direct	22.750s	3.044ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.662m	10.029ms	50	50	100.00
		spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	9.357m	93.736ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	16.240s	7.810ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	16.240s	7.810ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	4.569m	53.878ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	10.615m	83.313ms	50	50	100.00
V2	stress_all	spi_device_stress_all	11.657m	77.353ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.320s	36.818us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.430s	21.790us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	6.130s	878.849us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	6.130s	878.849us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.730s	63.920us	5	5	100.00
		spi_device_csr_rw	4.330s	121.345us	20	20	100.00
		spi_device_csr_aliasing	18.580s	4.019ms	5	5	100.00
		spi_device_same_csr_outstanding	5.630s	192.399us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.730s	63.920us	5	5	100.00
		spi_device_csr_rw	4.330s	121.345us	20	20	100.00
		spi_device_csr_aliasing	18.580s	4.019ms	5	5	100.00
		spi_device_same_csr_outstanding	5.630s	192.399us	20	20	100.00
V2		TOTAL			940	961	97.81
V2S	tl_intg_err	spi_device_sec_cm	2.740s	349.201us	5	5	100.00
		spi_device_tl_intg_err	23.400s	1.128ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.400s	1.128ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	5.033m	63.151ms	49	50	98.00
		TOTAL			1129	1151	98.09

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.45	98.99	96.22	83.25	89.36	98.41	95.66	99.26

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.49577823679232072732788126094899132837294843649093296389259558084093670957018
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @    897254 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[4])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    897254 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @    897254 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[900])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.107638566910294410881837151051383330391686025461721080390928968655958880098864
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   4432389 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[98])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   4432389 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   4432389 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[994])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:

Test spi_device_ram_cfg has 1 failures.

0.spi_device_ram_cfg.59516385260222170672999857068713661466493888669890872629382584782591178220706
Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

  UVM_ERROR @    923284 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @    923284 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
  UVM_ERROR @    986284 ps: (spi_device_ram_cfg_vseq.sv:26) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa70428 [101001110000010000101000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
  UVM_ERROR @    986284 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === ingress_ram_cfg (0xa70428 [101001110000010000101000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])

Job timed out after * minutes has 1 failures:
- Test spi_device_flash_mode_ignore_cmds has 1 failures.
  - 26.spi_device_flash_mode_ignore_cmds.35467317330691041685626996079570832078152865987121775303838952640339545162306
    Log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest/run.log
```
  Job timed out after 60 minutes
```