SPI_DEVICE/2P Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	9.515m	160.468ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.600s	99.465us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	3.880s	209.128us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	19.520s	2.272ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	15.650s	666.102us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	5.060s	323.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.880s	209.128us	20	20	100.00
		spi_device_csr_aliasing	15.650s	666.102us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	2.200s	36.254us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	3.650s	276.445us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	csb_read	spi_device_csb_read	2.360s	23.746us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	2.590s	16.364us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	1.750s	5.618us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	9.810s	1.100ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.810s	1.100ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	34.090s	147.263ms	50	50	100.00
		spi_device_tpm_sts_read	2.580s	177.121us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	43.860s	15.160ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	46.910s	30.240ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	39.430s	384.920ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	39.430s	384.920ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	cmd_info_slots	spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	cmd_read_status	spi_device_intercept	28.550s	3.801ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	cmd_read_jedec	spi_device_intercept	28.550s	3.801ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	cmd_read_sfdp	spi_device_intercept	28.550s	3.801ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	cmd_fast_read	spi_device_intercept	28.550s	3.801ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	cmd_read_pipeline	spi_device_intercept	28.550s	3.801ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	flash_cmd_upload	spi_device_upload	43.400s	71.172ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	2.114m	18.232ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	2.114m	18.232ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	2.114m	18.232ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	38.900s	11.216ms	50	50	100.00
		spi_device_read_buffer_direct	22.710s	2.324ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	2.114m	18.232ms	50	50	100.00
		spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	quad_spi	spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	dual_spi	spi_device_flash_all	5.540m	44.940ms	50	50	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	23.610s	4.031ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	23.610s	4.031ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	9.515m	160.468ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	8.819m	276.543ms	50	50	100.00
V2	stress_all	spi_device_stress_all	19.190m	143.710ms	50	50	100.00
V2	alert_test	spi_device_alert_test	2.380s	13.869us	50	50	100.00
V2	intr_test	spi_device_intr_test	2.380s	33.202us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.730s	265.126us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.730s	265.126us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.600s	99.465us	5	5	100.00
		spi_device_csr_rw	3.880s	209.128us	20	20	100.00
		spi_device_csr_aliasing	15.650s	666.102us	5	5	100.00
		spi_device_same_csr_outstanding	5.510s	243.494us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.600s	99.465us	5	5	100.00
		spi_device_csr_rw	3.880s	209.128us	20	20	100.00
		spi_device_csr_aliasing	15.650s	666.102us	5	5	100.00
		spi_device_same_csr_outstanding	5.510s	243.494us	20	20	100.00
V2		TOTAL			960	961	99.90
V2S	tl_intg_err	spi_device_sec_cm	2.870s	478.097us	5	5	100.00
		spi_device_tl_intg_err	18.770s	6.280ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	18.770s	6.280ms	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	8.006m	166.271ms	50	50	100.00
		TOTAL			1150	1151	99.91

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.46	99.02	96.31	83.25	89.36	98.46	95.65	99.21

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i) has 1 failures:
  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.105544556592027377114297751137817634635860921686213710115542566834617180135549
      Line 71, in log /nightly/runs/scratch/master/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4982401 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4982401 ps: (spi_device_ram_cfg_vseq.sv:19) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed (uvm_hdl_deposit(src_path, src_ram_cfg))
        UVM_ERROR @   4987401 ps: (spi_device_ram_cfg_vseq.sv:23) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === dst_ram_cfg (0x74bed0 [11101001011111011010000] vs 0xxxxxxx [xxxxxxxxxxxxxxxxxxxxxxxx])
        UVM_ERROR @   4987401 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.ram_cfg_i)