SPI_HOST Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	5.850m	71.058ms	50	50	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	5.000s	54.689us	5	5	100.00
V1	csr_rw	spi_host_csr_rw	5.000s	20.350us	20	20	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	7.000s	1.261ms	5	5	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	80.171us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	5.000s	33.657us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	5.000s	20.350us	20	20	100.00
		spi_host_csr_aliasing	5.000s	80.171us	5	5	100.00
V1	mem_walk	spi_host_mem_walk	5.000s	66.992us	5	5	100.00
V1	mem_partial_access	spi_host_mem_partial_access	5.000s	24.402us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	performance	spi_host_performance	6.000s	100.210us	50	50	100.00
V2	error_event_intr	spi_host_overflow_underflow	1.917m	4.141ms	50	50	100.00
		spi_host_error_cmd	5.000s	16.683us	50	50	100.00
		spi_host_event	8.583m	30.118ms	50	50	100.00
V2	clock_rate	spi_host_speed	21.000s	1.286ms	49	50	98.00
V2	speed	spi_host_speed	21.000s	1.286ms	49	50	98.00
V2	chip_select_timing	spi_host_speed	21.000s	1.286ms	49	50	98.00
V2	sw_reset	spi_host_sw_reset	3.650m	7.400ms	49	50	98.00
V2	passthrough_mode	spi_host_passthrough_mode	6.000s	3.329ms	50	50	100.00
V2	cpol_cpha	spi_host_speed	21.000s	1.286ms	49	50	98.00
V2	full_cycle	spi_host_speed	21.000s	1.286ms	49	50	98.00
V2	duplex	spi_host_smoke	5.850m	71.058ms	50	50	100.00
V2	tx_rx_only	spi_host_smoke	5.850m	71.058ms	50	50	100.00
V2	stress_all	spi_host_stress_all	1.800m	7.288ms	50	50	100.00
V2	spien	spi_host_spien	5.567m	9.016ms	49	50	98.00
V2	stall	spi_host_status_stall	5.333m	16.234ms	46	50	92.00
V2	Idlecsbactive	spi_host_idlecsbactive	30.000s	4.600ms	50	50	100.00
V2	data_fifo_status	spi_host_overflow_underflow	1.917m	4.141ms	50	50	100.00
V2	alert_test	spi_host_alert_test	5.000s	17.199us	50	50	100.00
V2	intr_test	spi_host_intr_test	5.000s	15.167us	50	50	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	6.000s	426.512us	20	20	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	6.000s	426.512us	20	20	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	5.000s	54.689us	5	5	100.00
		spi_host_csr_rw	5.000s	20.350us	20	20	100.00
		spi_host_csr_aliasing	5.000s	80.171us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	46.101us	20	20	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	5.000s	54.689us	5	5	100.00
		spi_host_csr_rw	5.000s	20.350us	20	20	100.00
		spi_host_csr_aliasing	5.000s	80.171us	5	5	100.00
		spi_host_same_csr_outstanding	5.000s	46.101us	20	20	100.00
V2		TOTAL			683	690	98.99
V2S	tl_intg_err	spi_host_tl_intg_err	6.000s	350.188us	20	20	100.00
		spi_host_sec_cm	5.000s	54.168us	5	5	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	6.000s	350.188us	20	20	100.00
V2S		TOTAL			25	25	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	55.050m	100.005ms	4	10	40.00
		TOTAL			827	840	98.45

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
96.26	96.74	93.21	98.69	94.40	88.02	100.00	96.86	91.56

Failure Buckets

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 6 failures:

  • Test spi_host_upper_range_clkdiv has 6 failures.

    • 1.spi_host_upper_range_clkdiv.39319523727637982117053894697339140195486568496825763535834422767088456683150
      Line 156, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100003841962 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xbd2c6914, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100003841962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • 3.spi_host_upper_range_clkdiv.101461950227122825190015903768402592184800527085325564629306768651644154111055
      Line 165, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 100004434070 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0xd9ec5c94, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
        UVM_INFO @ 100004434070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

    • ... and 4 more failures.

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=191) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 1.spi_host_status_stall.2875550432762588660601772914207158754947118213913243423664747913180139132223
      Line 952, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/1.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 15408127823 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x114126d4, Comparison=CompareOpEq, exp_data=0x0, call_count=191)
        UVM_INFO @ 15408127823 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=95) has 1 failures:

  • Test spi_host_speed has 1 failures.

    • 13.spi_host_speed.36432371715179902396864268877196874729282355029284230801350567944032465297423
      Line 638, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/13.spi_host_speed/latest/run.log

        UVM_FATAL @ 10217305766 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxqd (addr=0xfe65f754, Comparison=CompareOpEq, exp_data=0x0, call_count=95)
        UVM_INFO @ 10217305766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=94) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 16.spi_host_status_stall.85398328774500896930769827226604494476666422305252184348801315681107565746604
      Line 760, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/16.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10906519679 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0xfdfb1754, Comparison=CompareOpEq, exp_data=0x1, call_count=94)
        UVM_INFO @ 10906519679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=80) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 19.spi_host_status_stall.86277339225154500351720175473985095244596714022927526116403317427434272176288
      Line 714, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/19.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10113385896 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x9a5f1494, Comparison=CompareOpEq, exp_data=0x1, call_count=80)
        UVM_INFO @ 10113385896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=48) has 1 failures:

  • Test spi_host_sw_reset has 1 failures.

    • 26.spi_host_sw_reset.24698996318669764354966070667601138359838704570415779123586908085730876546332
      Line 290, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/26.spi_host_sw_reset/latest/run.log

        UVM_FATAL @ 10634012868 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.rxempty (addr=0x19d65e94, Comparison=CompareOpEq, exp_data=0x0, call_count=48)
        UVM_INFO @ 10634012868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=83) has 1 failures:

  • Test spi_host_status_stall has 1 failures.

    • 44.spi_host_status_stall.23800535771001721606988623469635355338740708387297818755635805734498530269292
      Line 711, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/44.spi_host_status_stall/latest/run.log

        UVM_FATAL @ 10593604458 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x336aac54, Comparison=CompareOpEq, exp_data=0x1, call_count=83)
        UVM_INFO @ 10593604458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:

  • Test spi_host_spien has 1 failures.

    • 46.spi_host_spien.69752894494654892197209299173206382391307563233284245570553865064766907382021
      Line 206, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/46.spi_host_spien/latest/run.log

        UVM_FATAL @ 17304992984 ps: (csr_utils_pkg.sv:627) [csr_utils::csr_spinwait] timeout spi_host_reg_block.status.ready (addr=0x28184a54, Comparison=CompareOpEq, exp_data=0x1, call_count=18)
        UVM_INFO @ 17304992984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---