SRAM_CTRL/MAIN Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.972m	1.288ms	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	2.100s	37.562us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.150s	15.740us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.680s	297.881us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	2.190s	21.885us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	7.100s	3.245ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.150s	15.740us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	21.885us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.512m	23.281ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.098m	9.815ms	50	50	100.00
V1		TOTAL			205	205	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	24.660m	28.560ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.840m	37.478ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	42.431m	597.896ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	21.597m	20.187ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.651m	18.079ms	50	50	100.00
V2	executable	sram_ctrl_executable	20.371m	18.870ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.526m	1.075ms	50	50	100.00
		sram_ctrl_partial_access_b2b	8.741m	56.175ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.675m	1.543ms	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.738m	3.266ms	50	50	100.00
		sram_ctrl_throughput_w_readback	1.727m	1.887ms	50	50	100.00
V2	regwen	sram_ctrl_regwen	21.938m	18.185ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	6.760s	4.781ms	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	2.490h	1.743s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	2.190s	14.475us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.740s	131.039us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.740s	131.039us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	2.100s	37.562us	5	5	100.00
		sram_ctrl_csr_rw	2.150s	15.740us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	21.885us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.390s	32.806us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	2.100s	37.562us	5	5	100.00
		sram_ctrl_csr_rw	2.150s	15.740us	20	20	100.00
		sram_ctrl_csr_aliasing	2.190s	21.885us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.390s	32.806us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	1.093m	29.392ms	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	2.150s	3.158us	0	5	0.00
		sram_ctrl_tl_intg_err	4.760s	1.877ms	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	2.150s	3.158us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.760s	1.877ms	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	21.938m	18.185ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	21.938m	18.185ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.150s	15.740us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	20.371m	18.870ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	20.371m	18.870ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	20.371m	18.870ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.651m	18.079ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	10.480s	3.036ms	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	1.093m	29.392ms	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	11.140s	5.972ms	35	50	70.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.972m	1.288ms	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.972m	1.288ms	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	20.371m	18.870ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	2.150s	3.158us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.651m	18.079ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	2.150s	3.158us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	2.150s	3.158us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.972m	1.288ms	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	2.150s	3.158us	0	5	0.00
V2S		TOTAL			119	145	82.07
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	3.604m	2.980ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1164	1190	97.82

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.07	99.29	93.01	85.18	100.00	98.07	98.59	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 14 failures:
- Test sram_ctrl_readback_err has 14 failures.
  - 5.sram_ctrl_readback_err.30302136457584596383835048505705745535324045303974329601972009168538242602152
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/5.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 1686456045 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x24) != exp (0xe)
  UVM_INFO @ 1686456045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.sram_ctrl_readback_err.112034479973912887368757617810591910255606636478947326818591300515569736357235
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/8.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 2740424621 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1) != exp (0x31)
  UVM_INFO @ 2740424621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 12 more failures.
Offending 'reqfifo_rvalid' has 6 failures:
- Test sram_ctrl_mubi_enc_err has 6 failures.
  - 12.sram_ctrl_mubi_enc_err.30754904614184589045382568417437517590267134136220190335180277663505877638908
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/12.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 2735847247 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 2735847247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 13.sram_ctrl_mubi_enc_err.54310130226798015613618128603145182242294901559684122205867388555931567967258
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/13.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @ 2628129540 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @ 2628129540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 4 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 3 failures:
- Test sram_ctrl_sec_cm has 3 failures.
  - 1.sram_ctrl_sec_cm.7166746044179561208349004423603313820457909095894609846241472830360948547407
    Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   3157611 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   3157611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 2.sram_ctrl_sec_cm.18393754980263496216519283534971167875486413400379963360528241617076377736562
    Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/2.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   1873664 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   1873664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 1 more failures.
Offending '(depth_o <= *'(Depth))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 0.sram_ctrl_sec_cm.91708832179264404374362702086807504909912735876398817247691119580234845245348
    Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(depth_o <= 2'(Depth))'
  UVM_ERROR @   3348959 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
  UVM_INFO @   3348959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$isunknown(rdata_o))' has 1 failures:
- Test sram_ctrl_sec_cm has 1 failures.
  - 3.sram_ctrl_sec_cm.113383939081726356737428579567098451507410721770535800768614526451889435210616
    Line 96, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/3.sram_ctrl_sec_cm/latest/run.log
```
      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @   9843201 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
  UVM_INFO @   9843201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@6127) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_readback_err has 1 failures.

46.sram_ctrl_readback_err.90038496841598909895883084234237521179330776687464529457612616247878480865950
Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/46.sram_ctrl_readback_err/latest/run.log

  UVM_ERROR @ 2752024911 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@6127) { a_addr: 'h46a9cafc  a_data: 'h6a  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h1  a_user: 'h26c75  d_param: 'h0  d_source: 'h2  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2752024911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---