SRAM_CTRL/RET Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: `97d23b4`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	1.630m	289.664us	50	50	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.970s	42.465us	5	5	100.00
V1	csr_rw	sram_ctrl_csr_rw	2.130s	14.600us	20	20	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	3.600s	466.894us	5	5	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.960s	51.737us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	4.440s	219.381us	16	20	80.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	2.130s	14.600us	20	20	100.00
		sram_ctrl_csr_aliasing	1.960s	51.737us	5	5	100.00
V1	mem_walk	sram_ctrl_mem_walk	14.540s	3.101ms	50	50	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	8.070s	2.868ms	50	50	100.00
V1		TOTAL			201	205	98.05
V2	multiple_keys	sram_ctrl_multiple_keys	20.476m	18.726ms	50	50	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	6.909m	4.466ms	50	50	100.00
V2	bijection	sram_ctrl_bijection	1.454m	5.575ms	50	50	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	28.863m	22.720ms	50	50	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	15.450s	1.974ms	50	50	100.00
V2	executable	sram_ctrl_executable	18.989m	18.013ms	50	50	100.00
V2	partial_access	sram_ctrl_partial_access	1.626m	423.574us	50	50	100.00
		sram_ctrl_partial_access_b2b	8.271m	42.231ms	50	50	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.606m	139.747us	50	50	100.00
		sram_ctrl_throughput_w_partial_write	1.558m	156.285us	50	50	100.00
		sram_ctrl_throughput_w_readback	1.629m	964.285us	50	50	100.00
V2	regwen	sram_ctrl_regwen	23.401m	46.079ms	50	50	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.980s	42.183us	50	50	100.00
V2	stress_all	sram_ctrl_stress_all	1.136h	1.254s	50	50	100.00
V2	alert_test	sram_ctrl_alert_test	3.890s	38.173us	50	50	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	5.880s	604.805us	20	20	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	5.880s	604.805us	20	20	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.970s	42.465us	5	5	100.00
		sram_ctrl_csr_rw	2.130s	14.600us	20	20	100.00
		sram_ctrl_csr_aliasing	1.960s	51.737us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.130s	53.442us	20	20	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.970s	42.465us	5	5	100.00
		sram_ctrl_csr_rw	2.130s	14.600us	20	20	100.00
		sram_ctrl_csr_aliasing	1.960s	51.737us	5	5	100.00
		sram_ctrl_same_csr_outstanding	2.130s	53.442us	20	20	100.00
V2		TOTAL			790	790	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	5.760s	437.378us	20	20	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	3.840s	4.961us	0	5	0.00
		sram_ctrl_tl_intg_err	4.020s	525.482us	20	20	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	3.840s	4.961us	0	5	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	4.020s	525.482us	20	20	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	23.401m	46.079ms	50	50	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	23.401m	46.079ms	50	50	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	2.130s	14.600us	20	20	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	18.989m	18.013ms	50	50	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	18.989m	18.013ms	50	50	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	18.989m	18.013ms	50	50	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	15.450s	1.974ms	50	50	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.030s	36.255us	44	50	88.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	5.760s	437.378us	20	20	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.010s	30.420us	40	50	80.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	1.630m	289.664us	50	50	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	1.630m	289.664us	50	50	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	18.989m	18.013ms	50	50	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	3.840s	4.961us	0	5	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	15.450s	1.974ms	50	50	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	3.840s	4.961us	0	5	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	3.840s	4.961us	0	5	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	1.630m	289.664us	50	50	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	3.840s	4.961us	0	5	0.00
V2S		TOTAL			124	145	85.52
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.925m	1.900ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			1165	1190	97.90

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.04	99.26	93.01	85.10	100.00	98.03	98.58	98.33

Failure Buckets

UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 10 failures:
- Test sram_ctrl_readback_err has 10 failures.
  - 2.sram_ctrl_readback_err.80350728011846299541771747167779603611193091314552825153140998465060223760518
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @ 321966451 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x63) != exp (0x34)
  UVM_INFO @ 321966451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 8.sram_ctrl_readback_err.68300202663533361193950565667364331381341326631003886839436942894734374544174
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/8.sram_ctrl_readback_err/latest/run.log
```
  UVM_ERROR @  94948702 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x1e) != exp (0x3e)
  UVM_INFO @  94948702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 8 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 5 failures:
- Test sram_ctrl_sec_cm has 5 failures.
  - 0.sram_ctrl_sec_cm.68263579536204034677394137736258184405547126931143868831254695726011350459470
    Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   4961288 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   4961288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 1.sram_ctrl_sec_cm.58305716730238109087902983429071811339644065284693086543314370854347530099796
    Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @   8173567 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
  UVM_INFO @   8173567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
Offending 'reqfifo_rvalid' has 5 failures:
- Test sram_ctrl_mubi_enc_err has 5 failures.
  - 5.sram_ctrl_mubi_enc_err.13088344575906466828889414085869130338298788585783125759655664715654484294372
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/5.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  89399099 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  89399099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 9.sram_ctrl_mubi_enc_err.84958364023998776791698877251744731107134627761569339512421542536761546009412
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/9.sram_ctrl_mubi_enc_err/latest/run.log
```
      Offending 'reqfifo_rvalid'
  UVM_ERROR @  47453875 ps: (tlul_adapter_sram.sv:640) [ASSERT FAILED] rvalidHighReqFifoEmpty
  UVM_INFO @  47453875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - ... and 3 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: * has 2 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 2.sram_ctrl_csr_mem_rw_with_rand_reset.103388355477838713237897453741631904115534337425344694339217544805428689766419
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  44711652 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  44711652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
  - 17.sram_ctrl_csr_mem_rw_with_rand_reset.107119898778692756193434403458478377690579181293807357082103893356130867898771
    Line 99, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/17.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  38884777 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (8 [0x8] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated.success reset value: 0x9
  UVM_INFO @  38884777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.sram_ctrl_csr_mem_rw_with_rand_reset.45579284130006535811904534171292965865844683903064794452931621066468749614713
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  28549181 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status.scr_key_valid reset value: 0x0
  UVM_INFO @  28549181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status reset value: * has 1 failures:
- Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.
  - 14.sram_ctrl_csr_mem_rw_with_rand_reset.85252414194758502289740752131969416131397399553246272201875986283855730729851
    Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/14.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  88467966 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (56 [0x38] vs 0 [0x0]) Regname: sram_ctrl_regs_reg_block.status reset value: 0x0
  UVM_INFO @  88467966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4721) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test sram_ctrl_mubi_enc_err has 1 failures.

23.sram_ctrl_mubi_enc_err.58925232460033825626132605373641135580053817108363287748088245623835450273049
Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/23.sram_ctrl_mubi_enc_err/latest/run.log

  UVM_ERROR @  30044292 ps: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface sram_ctrl_prim_reg_block, TL item: req: (cip_tl_seq_item@4721) { a_addr: 'hf28d39dc  a_data: 'h65  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'hb1  a_opcode: 'h1  a_user: 'h27f6d  d_param: 'h0  d_source: 'hb1  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @  30044292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---