UART Simulation Results

Sunday April 20 2025 00:13:53 UTC

GitHub Revision: 97d23b4

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	38.180s	10.530ms	50	50	100.00
V1	csr_hw_reset	uart_csr_hw_reset	2.190s	47.617us	5	5	100.00
V1	csr_rw	uart_csr_rw	2.270s	15.170us	20	20	100.00
V1	csr_bit_bash	uart_csr_bit_bash	3.710s	58.025us	5	5	100.00
V1	csr_aliasing	uart_csr_aliasing	2.360s	147.109us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	2.830s	58.919us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	2.270s	15.170us	20	20	100.00
		uart_csr_aliasing	2.360s	147.109us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	base_random_seq	uart_tx_rx	3.395m	101.617ms	50	50	100.00
V2	parity	uart_smoke	38.180s	10.530ms	50	50	100.00
		uart_tx_rx	3.395m	101.617ms	50	50	100.00
V2	parity_error	uart_intr	18.132m	732.638ms	50	50	100.00
		uart_rx_parity_err	6.442m	228.648ms	50	50	100.00
V2	watermark	uart_tx_rx	3.395m	101.617ms	50	50	100.00
		uart_intr	18.132m	732.638ms	50	50	100.00
V2	fifo_full	uart_fifo_full	18.061m	205.528ms	50	50	100.00
V2	fifo_overflow	uart_fifo_overflow	6.859m	86.518ms	50	50	100.00
V2	fifo_reset	uart_fifo_reset	5.402m	125.050ms	300	300	100.00
V2	rx_frame_err	uart_intr	18.132m	732.638ms	50	50	100.00
V2	rx_break_err	uart_intr	18.132m	732.638ms	50	50	100.00
V2	rx_timeout	uart_intr	18.132m	732.638ms	50	50	100.00
V2	perf	uart_perf	20.292m	28.880ms	50	50	100.00
V2	sys_loopback	uart_loopback	30.560s	11.152ms	50	50	100.00
V2	line_loopback	uart_loopback	30.560s	11.152ms	50	50	100.00
V2	rx_noise_filter	uart_noise_filter	9.071m	110.636ms	50	50	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.823m	57.275ms	50	50	100.00
V2	tx_overide	uart_tx_ovrd	39.770s	6.780ms	50	50	100.00
V2	rx_oversample	uart_rx_oversample	1.220m	7.472ms	50	50	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	20.858m	164.548ms	50	50	100.00
V2	stress_all	uart_stress_all	25.462m	111.833ms	50	50	100.00
V2	alert_test	uart_alert_test	2.220s	19.917us	50	50	100.00
V2	intr_test	uart_intr_test	2.380s	21.527us	50	50	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	4.110s	123.963us	20	20	100.00
V2	tl_d_illegal_access	uart_tl_errors	4.110s	123.963us	20	20	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	2.190s	47.617us	5	5	100.00
		uart_csr_rw	2.270s	15.170us	20	20	100.00
		uart_csr_aliasing	2.360s	147.109us	5	5	100.00
		uart_same_csr_outstanding	2.490s	120.640us	20	20	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	2.190s	47.617us	5	5	100.00
		uart_csr_rw	2.270s	15.170us	20	20	100.00
		uart_csr_aliasing	2.360s	147.109us	5	5	100.00
		uart_same_csr_outstanding	2.490s	120.640us	20	20	100.00
V2		TOTAL			1090	1090	100.00
V2S	tl_intg_err	uart_sec_cm	2.300s	119.565us	5	5	100.00
		uart_tl_intg_err	2.910s	274.925us	20	20	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.910s	274.925us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	1.709m	38.401ms	99	100	99.00
V3		TOTAL			99	100	99.00
		TOTAL			1319	1320	99.92

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.79	99.17	98.25	91.55	--	98.15	100.00	99.62

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 93.uart_stress_all_with_rand_reset.35598788806486070134416369763067808630882644343830521510285983003438892214922
      Line 136, in log /nightly/runs/scratch/master/uart-sim-vcs/93.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7188316585 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 7188316585 ps: (cip_base_vseq.sv:832) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Issuing reset for run 5/5
        UVM_INFO @ 7188508895 ps: (cip_base_vseq.sv:852) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]
        Stress w/ reset is done for run 5/5